HD64F3670 Datasheet, PDF (16/305 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Figure 5-6 Example of Incorrect Board Design............................................................................64
Section 6 Power-down Modes
Figure 6-1 Mode Transition Diagram ...........................................................................................69
Section 7 ROM
Figure 7-1 Flash Memory Block Configuration............................................................................74
Figure 7-2 Programming/Erasing Flowchart Example in User Program Mode............................80
Figure 7-3 Program/Program-Verify Flowchart ...........................................................................82
Figure 7-4 Erase/Erase-Verify Flowchart .....................................................................................85
Section 9 I/O Ports
Figure 9-1 Port 1 Pin Configuration .............................................................................................89
Figure 9-2 Port 2 Pin Configuration .............................................................................................94
Figure 9-3 Port 5 Pin Configuration .............................................................................................96
Figure 9-4 Port 7 Pin Configuration ...........................................................................................101
Figure 9-5 Port 8 Pin Configuration ...........................................................................................104
Figure 9-6 Port B Pin Configuration...........................................................................................107
Section 10 Timer V
Figure 10-1 Block Diagram of Timer V .....................................................................................110
Figure 10-2 Increment Timing with Internal Clock....................................................................116
Figure 10-3 Increment Timing with External Clock...................................................................116
Figure 10-4 OVF Set Timing......................................................................................................117
Figure 10-5 CMFA and CMFB Set Timing................................................................................117
Figure 10-6 TMOV Output Timing ............................................................................................117
Figure 10-7 Clear Timing by Compare Match............................................................................117
Figure 10-8 Clear Timing by TMRIV Input ...............................................................................118
Figure 10-9 Pulse Output Example.............................................................................................119
Figure 10-10 Example of Pulse Output Synchronized to TRGV Input ......................................120
Figure 10-11 Contention between TCNTV Write and Clear ......................................................121
Figure 10-12 Contention between TCORA Write and Compare Match.....................................122
Figure 10-13 Internal Clock Switching and TCNTV Operation.................................................122
Section 11 Timer W
Figure 11-1 Timer W Block Diagram.........................................................................................125
Figure 11-2 Free-Running Counter Operation............................................................................134
Figure 11-3 Periodic Counter Operation.....................................................................................135
Figure 11-4 0 and 1 Output Example(TOA = 0, TOB = 1).........................................................135
Figure 11-5 Toggle Output Example (TOA = 0, TOB = 1) ........................................................136
Figure 11-6 Toggle Output Example (TOA = 0, TOB = 1) ........................................................136
Figure 11-7 Input Capture Operating Example...........................................................................137
Figure 11-8 Buffer Operation Example (Input Capture).............................................................137
Rev. 1.0, 03/01, page xvi of xxiv