HD64F3670 Datasheet, PDF (103/305 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Table 7-2 Boot Mode Operation
Host Operation
Item
Processing Contents
Bit rate
adjustment
Continuously transmits data H'00 at
specified bit rate.
Transmits data H'55 when data H'00
is received and no error occurs.
Transfer of
programming control
program
Transfer of
programming control
program (repeated for
N times)
Flash memory erase
Transmits number of bytes (N) of
programming control program to be
transferred as 2-byte data (low-order
byte following high-order byte)
Transmits 1-byte of programming
control program
Execution of
Programming
control program
LSI Operation
Processing Contents
Branches to boot program at reset-start.
· Measures low-level period of receive data H'00.
· Calculates bit rate and sets it in BRR of SCI3.
· Transmits data H'00 to the host to indicate that the
adjustment has ended.
Transmits 1-byte data H'AA to the host when data
H'55 is received.
Echobacks the 2-byte received data to host.
Echobacks received data to host and also
transfers it to RAM.
Checks flash memory data, erases all flash memory
blocks in case of written data existing, and transmits
data H'AA to host. (If erase could not be done,
transmits data H'FF to host and aborts operation.)
Branches to programming control program
transferred to on-chip RAM and starts execution.
Table 7-3 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is
Possible
Host Bit Rate
19,200 bps
9,600 bps
4,800 bps
2,400 bps
System Clock Frequency Range of LSI
16MHz
8 to 16 MHz
4 to 16 MHz
2 to 16 MHz
Rev. 1.0, 03/01, page 79 of 280