HD64F3670 Datasheet, PDF (175/305 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Bit Bit Name Initial Value R/W
0 WRST 0
R/W
Description
Watchdog Timer Reset
[Setting condition]
When TCWD overflows and an internal reset signal is
generated
[Clearing condition]
• Reset by RES pin
• When 0 is written to the WRST bit while writing 0 to the
B0WI bit when the TCSRWE bit=1
12.2.2 Timer Counter WD(TCWD)
TCWD is an 8-bit readable/writable up-counter. The WRST bit in TCSRWD is set to 1, when
TCWD overflows from H'FF to H'00. TCWD is initialized to H'00.
12.2.3 Timer Mode Register WD(TMWD)
TMWD is an 8-bit readable/writable register that selects the input clock.
Bit Bit Name Initial Value R/W
7−
1
−
6−
1
−
5−
1
−
4−
1
−
3 CKS3
1
R/W
2 CKS2
1
R/W
1 CKS1
1
R/W
0 CKS0
1
R/W
Legend X: Don't care.
Description
Reserved
These bits are always read as 1.
Clock Select 3 to 0
Select the clock to be input to TCWD.
1000: Internal clock: counts on φ/64
1001: Internal clock: counts on φ/128
1010: Internal clock: counts on φ/256
1011: Internal clock: counts on φ/512
1100: Internal clock: counts on φ/1024
1101: Internal clock: counts on φ/2048
1110: Internal clock: counts on φ/8192
1111: Internal clock: counts on φ
0XXX: Internal resonator
For the internal oscillator overflow periods, see section 16,
Electrical Characteristics.
Rev. 1.0, 03/01, page 151 of 280