HD64F3670 Datasheet, PDF (185/305 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Bit Bit Name
4 FER
3 PER
2 TEND
1 MPBR
0 MPBT
Initial Value R/W
0
R/W
0
R/W
0
R
0
R
0
R/W
Description
Framing Error
[Setting condition]
• When a framing error occurs in reception
[Clearing condition]
• When 0 is written to FER after reading FER =
1
Parity Error
[Setting condition]
• When a parity error is detected during
reception
[Clearing condition]
• When 0 is written to PER after reading PER =
1
Transmit End
[Setting conditions]
• When the TE bit in SCR3 is 0
• When TDRE = 1 at transmission of the last bit
of a 1-byte serial transmit character
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE
=1
• When the transmit data is written to TDR
Multiprocessor Bit Receive
MPBR stores the multiprocessor bit in the receive
character data. When the RE bit in SCR3 is
cleared to 0 its previous state is retained.
Multiprocessor Bit Transfer
MPBT stores the multiprocessor bit to be added to
the transmit character data.
Rev. 1.0, 03/01, page 161 of 280