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HD64F3670 Datasheet, PDF (48/305 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer | |||
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Table 2-8 System Control Instructions
Instruction Size* Function
TRAPA
â
Starts trap-instruction exception handling.
RTE
â
Returns from an exception-handling routine.
SLEEP
â
Causes a transition to a power-down state.
LDC
B/W
(EAs) â CCR
Moves the source operand contents to the CCR. The CCR size is one
byte, but in transfer from memory, data is read by word access.
STC
B/W
CCR â (EAd), EXR â (EAd)
Transfers the CCR contents to a destination location. The condition code
register size is one byte, but in transfer to memory, data is written by
word access.
ANDC
B
CCR ⧠#IMM â CCR, EXR ⧠#IMM â EXR
Logically ANDs the CCR with immediate data.
ORC
B
CCR ⨠#IMM â CCR, EXR ⨠#IMM â EXR
Logically ORs the CCR with immediate data.
XORC
B
CCR â #IMM â CCR, EXR â #IMM â EXR
Logically XORs the CCR with immediate data.
NOP
â
PC + 2 â PC
Only increments the program counter.
Note: * Refers to the operand size.
B: Byte
W: Word
Rev. 1.0, 03/01, page 24 of 280
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