HD64F3670 Datasheet, PDF (173/305 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Section 12 Watchdog Timer
The watchdog timer(WDT) is an 8-bit timer that can generate an internal reset signal for this LSI
if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow.
The block diagram of the WDT is shown in figure 12-1.
Internal
oscillator
ø
CLK
PSS
TCSRWD
TCWD
TMWD
Legend:
TCSRWD: Timer control/status register WD
TCWD: Timer counter WD
PSS:
Prescaler S
TMWD: Timer mode register WD
Figure 12-1 Block Diagram of WDT
Internal reset
signal
12.1 Features
• Selectable from nine counter input clocks.
Eight clock sources (φ/64, φ/128, φ/256, φ/512, φ/1024, φ/2048, φ/4096, φ/8192) or the internal
oscillator can be selected as the timer-counter clock. When the internal oscillator is selected, it
can operate as the watchdog timer in any operating mode, except in standby mode.
• Reset signal generated on counter overflow
An overflow period of 1 to 256 times the selected clock can be set.
12.2 Register Descriptions
The WDT has the following registers. For details on register addresses and register states during
each process, refer to appendix B, Internal I/O Register.
• Timer control/status register WD(TCSRWD)
• Timer counter WD(TCWD)
• Timer mode register WD(TMWD)
Rev. 1.0, 03/01, page 149 of 280