HD64F3670 Datasheet, PDF (18/305 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Figure 13-14 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
(Clocked Synchronous Mode) ...............................................................................182
Figure 13-15 Example of Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A) ...........................................184
Figure 13-16 Sample Multiprocessor Serial Transmission Flowchart........................................185
Figure 13-17 Sample Multiprocessor Serial Reception Flowchart (1)........................................ 187
Figure 13-17 Sample Multiprocessor Serial Reception Flowchart (2)........................................ 188
Figure 13-18 Example of SCI3 Operation in Reception Using Multiprocessor Format
(Example with 8-Bit Data, MultiprocessorBit, One Stop Bit) ...............................189
Figure 13-19 Receive Data Sampling Timing in Asynchronous Mode ......................................192
Section 14 A/D Converter
Figure 14-1 Block Diagram of A/D Converter ...........................................................................194
Figure 14-2 A/D Conversion Timing..........................................................................................200
Figure 14-3 External Trigger Input Timing ................................................................................201
Figure 14-4 A/D Conversion Precision Definitions (1) ..............................................................202
Figure 14-5 A/D Conversion Precision Definitions (2) ..............................................................203
Figure 14-6 Analog Input Circuit Example ................................................................................204
Section 15 Power Supply Circuit
Figure 15-1 Power Supply Connection when Internal Step-Down Circuit Is Used....................205
Figure 15-2 Power Supply Connection when Internal Step-Down Circuit Is Not Used .............206
Section 16 Electrical Characteristics
Figure 16-1 System Clock Input Timing ....................................................................................221
Figure 16-2 RES Low Width Timing .........................................................................................221
Figure 16-3 Input Timing ...........................................................................................................221
Figure 16-4 SCK3 Input Clock Timing ......................................................................................222
Figure 16-5 Serial Interface 3 Synchronous Mode Input/Output Timing ...................................222
Figure 16-6 Output Load Condition ...........................................................................................223
Appendix C I/O Port Block Diagrams
Figure C.1 Port 1 Block Diagram (P17) .....................................................................................260
Figure C.2 Port 1 Block Diagram (P14) .....................................................................................261
Figure C.3 Port 1 Block Diagram (P16, P15, P12, P10).............................................................262
Figure C.4 Port 1 Block Diagram (P11) .....................................................................................263
Figure C.5 Port 2 Block Diagram (P22) .....................................................................................264
Figure C.6 Port 2 Block Diagram (P21) .....................................................................................265
Figure C.7 Port 2 Block Diagram (P20) .....................................................................................266
Figure C.8 Port 5 Block Diagram (P57, P56) .............................................................................267
Figure C.9 Port 5 Block Diagram (P55) .....................................................................................268
Figure C.10 Port 5 Block Diagram (P54 to P50) ........................................................................269
Figure C.11 Port 7 Block Diagram (P76) ...................................................................................270
Rev. 1.0, 03/01, page xviii of xxiv