HD64F3670 Datasheet, PDF (54/305 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Table 2-12 Effective Address Calculation (1)
No Addressing Mode and Instruction Format
1 Register direct(Rn)
op rm rn
2 Register indirect(@ERn)
op
r
3 Register indirect with displacement
@(d:16,ERn) or @(d:24,ERn)
op
r
disp
Effective Address Calculation
31
0
General register contents
31
0
General register contents
31
Sign extension
0
disp
4 Register indirect with post-increment or
pre-decrement
31
0
•Register indirect with post-increment @ERn+
General register contents
op
r
•Register indirect with pre-decrement @-ERn
1, 2, or 4
31
0
General register contents
op
r
1, 2, or 4
The value to be added or subtracted is 1 when the
operand is byte size, 2 for word size, and 4 for
longword size.
Effective Address (EA)
Operand is general register contents.
23
0
23
0
23
0
23
0
Rev. 1.0, 03/01, page 30 of 280