HD64F3670 Datasheet, PDF (82/305 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

4.1.4 Break Data Registers (BDRH, BDRL)
BDRH, BDRL are 16-bit read/write registers that set the data for generating an address break
interrupt. BDRH is compared with the upper 8-bit data bus. BDRL is compared with the lower 8-
bit data bus. When memory or registers are accessed by byte, the upper 8-bit data bus is used for
even and odd addresses in the data transmission. Therefore, comparison data must be set in
BDRH for byte access. For word access, the data bus used depends on the address. See section
4.1.1, Address Break Control Register, for details. The initial value of this register is undefined.
4.2 Operation
When the ABIE bit in ABRKSR is set to 1, if the ABIF bit in ABRKSR is set to 1 by the
combination of the address set in BAR, the data set in BDR, and the conditions set in ABRKCR,
the address break function generates an interrupt request to the CPU. When the interrupt request
is accepted, interrupt exception handling starts after the instruction being executed ends. The
address break interrupt is not masked because of the I bit in CCR of the CPU.
Figures 4-2 show the operation examples of the address break interrupt setting.
When the address break is specified in instruction execution cycle
Register setting
• ABRKCR = H'80
• BAR = H'025A
Program
0258 NOP
* 025A NOP
025C MOV.W @H'025A,R0
0260 NOP
0262 NOP
:
:
Underline indicates the address
to be stacked.
φ
Address
bus
Interrupt
request
NOP NOP MOV MOV
instruc- instruc- instruc- instruc-
tion
tion tion 1 tion 2 Internal
prefetch prefetch prefetch prefetch processing
Stack save
0258 025A 025C 025E
Interrupt acceptance
SP-2 SP-4
Figure 4-2 Address Break Interrupt Operation Example (1)
Rev. 1.0, 03/01, page 58 of 280