HD64F3670 Datasheet, PDF (273/305 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Instruction Mnemonic
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
Addr. Read Operation Access Access Operation
I
J
K
L
M
N
RTE
RTE
2
2
2
RTS
RTS
2
1
2
SHAL
SHAL.B Rd
1
SHAR
SHAR.B Rd
1
SHLL
SHLL.B Rd
1
SHLR
SHLR.B Rd
1
SLEEP SLEEP
1
STC
STC CCR, Rd
1
SUB
SUB.B Rs, Rd
1
SUB.W Rs, Rd
1
SUBS
SUBS.W #1, Rd
1
SUBS.W #2, Rd
1
POP
POP Rd
1
1
2
PUSH
PUSH Rs
1
1
2
SUBX
SUBX.B #xx:8, Rd 1
SUBX.B Rs, Rd
1
XOR
XOR.B #xx:8, Rd 1
XOR.B Rs, Rd
1
XORC
XORC #xx:8, CCR 1
Note: n: specified value in R4L. The source and destination operands are accessed n + 1 times
respectively.
Rev. 1.0, 03/01, page 249 of 280