CN8478 Datasheet, PDF (96/221 Pages) Conexant Systems, Inc – Multichannel Synchronous Communications Controller (MUSYCC)

5.0 Memory Organization
5.2 Descriptors
CN8478/CN8474A/CN8472A/CN8471A
Multichannel Synchronous Communications Controller (MUSYCC™)
5.2.1 Host Interface Level Descriptors
5.2.1.1 Global
Configuration Descriptor
Host interface-level descriptors contain information necessary to configure the
global registers. This information applies to the entire device, including all
channel groups, serial ports, and channels.
The Global Configuration Descriptor specifies configuration information
applying to the entire device including all channel groups, serial ports, and
channels.
Memory space is reserved for the Global Configuration Descriptor within
each Channel Group Descriptor. By convention, the values corresponding to
Channel Group 0 (a group present in all versions of MUSYCC) provides the
correct data. The host coordinates how this data is transferred into MUSYCC by:
• Instructing MUSYCC to read the Channel Group 0 Global Configuration
Descriptor when setting the global data.
• Copying the Channel Group 0 Global Configuration Descriptor to all other
supported Channel Group Descriptors and requesting a global
initialization service request operation for any supported channel groups.
The components and their descriptions are listed in Table 5-6.
Table 5-6. Global Configuration Descriptor (1 of 2)
Bit
Field
Name
Value
Description
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14:12
TCLKACT7
TCLKACT6
TCLKACT5
TCLKACT4
RCLKACT7
RCLKACT6
RCLKACT5
RCLKACT4
TCLKACT3
TCLKACT2
TCLKACT1
TCLKACT0
RCLKACT3
RCLKACT2
RCLKACT1
RCLKACT0
RSVD
BLAPSE[2:0]
11
ECKEN
Transmit and Receive Line Clock Activity Indicator.
0,1,2, 3, 4, 5, 6, or 7 corresponds to a channel group number.
Read Only. Reset to 0 after each read.
Each indicator bit is cleared when the respective channel group is reset via PCI
Reset, Soft Group Reset, or Soft Chip Reset.
The TCLKACTx corresponds to TCLKx line clock.
The RCLKACTx corresponds to RCLKx line clock.
The indicator is set to 1 on the second rising edge of the corresponding serial
interface line clock, and the previous value for the indicator bit was 0.
If multiple channel groups are mapped to a single serial port, one clock is driving
each channel group. The indicator bits reflect the activity of the clock driving the
channel group.
If MUSYCC does not detect a line clock, the value of the indicator bit(s) remain at
the reset value 0.
Reading from channel group RAM during the absence of a line clock results in the
dword DEADACCEh (dead access) being returned. Writing to channel group RAM
during the absence of a line clock results in the write being ignored.
0
Reserved.
0–7 Expansion Bus Access Interval. MUSYCC waits BLAPSE+4 number of ECLK periods
immediately after relinquishing the bus. This wait ensures that all the bus grant signals
driven by the bus arbiter have sufficient time to be deasserted as a result of bus
request signals being deasserted by MUSYCC.
0
Expansion Bus Clock Disabled. ECLK output is three-stated.
1
Expansion Bus Clock Enabled. MUSYCC redrives and inverts PCLK input onto ECLK
output pin.
5-10
Conexant
100660E