CN8478 Datasheet, PDF (136/221 Pages) Conexant Systems, Inc – Multichannel Synchronous Communications Controller (MUSYCC)

6.0 Basic Operation
6.1 Reset
CN8478/CN8474A/CN8472A/CN8471A
Multichannel Synchronous Communications Controller (MUSYCC™)
6.1.2 Soft Chip Reset
A Soft Chip Reset (SCR) is a device-wide reset without the host interface’s PCI
state being reset. Serial interface operations and EBUS operations are stopped.
The soft chip reset state is entered in one of two ways:
• as a result of the PCI reset
• as a result of a soft chip reset service request
A SCR performs the following functions:
• Sets all bits to 0 in Global Configuration Descriptor register except for
PORTMAP [1:0], which retains its current value.
• Sets all bits to 0 in Interrupt Status register, including NEXTINT,
INTFULL, and INTCNT.
• Sets all bits to 0 in Group Configuration Descriptor register except
MSKCOFA and MSKOOF which are set to 1. Thus, all supported groups
(both directions) are disabled.
• Resets the interrupt write index to 0. Hence, the next interrupt is written at
the location pointed to by the value of Interrupt Queue Pointer. (Present
values of the Interrupt Queue Pointer and Interrupt Queue Length remain
intact.)
• Deactivates all 32 channels (both directions) of each group. This action
remains pending until two serial port clocks have been applied on the
respective channel group input.
• Sets all bits to 0 in the following registers:
1. Port Configuration Descriptor
2. Memory Protection Descriptor
3. Message Length Descriptor
4. Service Request Descriptor
NOTE: SCR does not affect any PCI configuration register contents.
After the host requests a SCR by writing to the Service Request Descriptor,
MUSYCC does not acknowledge SCR execution with any Service Request
Acknowledge (SACK) Interrupt Descriptor. Although no SACK is generated,
MUSYCC will have completed execution of the transmit and receive serial port
SCR functions after two clock pulses are applied to the respective TCLK and
RCLK serial port inputs. These serial port clocks do not have to be present when
the SCR write occurs.
When writing an SCR service request, the host must ensure at least one PCI
bus clock cycle has elapsed before writing another service request. To meet this
minimum elapsed service request write timing interval, it is recommended that
the host follow any SCR write with another service request read from the same
address. Reading back the Service Request Descriptor prevents a PCI burst write
from sequentially writing different values into that descriptor.
6-2
Conexant
100660E