CN8478 Datasheet, PDF (64/221 Pages) Conexant Systems, Inc – Multichannel Synchronous Communications Controller (MUSYCC)

3.0 Expansion Bus (EBUS)
3.1 Operation
3.1.4 Interrupt
CN8478/CN8474A/CN8472A/CN8471A
Multichannel Synchronous Communications Controller (MUSYCC™)
When a device connected to the EBUS drives the EINT* signal, MUSYCC
carries this signal through to the PCI interrupt line, INTB*. Thus, peripheral
devices can interrupt the host processor.
In MUSYCC’s Function 1 PCI Configuration Space (the EBUS function), the
Interrupt Pin bit field indicates that the INTB* PCI interrupt be asserted for
interrupts sourced by devices connected to the EBUS (see Table 2-16, Register
15, Address 3Ch). Also, the Interrupt Line bit field in the same register is set up
by the system initialization software to indicate which host interrupt controller
input pin is to be connected to MUSYCC’s INTB* pin.
3.1.5 Address Duration
MUSYCC can extend the duration the address bits are valid for any EBUS
address phase by specifying a value from 0–3 in ALAPSE bit field (refer to
Table 5-6, Global Configuration Descriptor). The value specifies the additional
ECLK periods the address bits remain asserted. That is, a value of 0 specifies the
address remains asserted for one ECLK period, and a value of 3 specifies the
address remains asserted for four ECLK periods. Disabling the ECLK signal
output does not affect the delay mechanism. Refer to the timing diagrams in
Section 7.2.4 for more details.
Both pre- and post-address cycles are always present during the address phase
of an EBUS cycle. The post-address cycle is one PCI period long and provides
MUSYCC time to transition between the address phase and the following data
phase. The pre- and post-address cycles are not included in the address duration.
3.1.6 Data Duration
MUSYCC can extend the duration that the data bits are valid for any EBUS data
phase by specifying a value from 0–7 in ELAPSE bit field (refer to
Table 5-6, Global Configuration Descriptor). The value specifies the additional
ECLK periods the data bits remain asserted. That is, a value of 0 specifies the
data that remains asserted for one ECLK period, and a value of 7 specifies the
data that remains asserted for eight ECLK periods. Disabling the ECLK signal
output does not affect the delay mechanism. Refer to the timing diagrams in
Section 7.2.4 for more details.
A pre-data and post-data cycle are always present during the data phase of an
EBUS cycle. The pre-data cycle is one PCI period long and provides MUSYCC
setup and hold time for the data signals. The post-data cycle is one ECLK period
long and provides MUSYCC time to transition between the data phase and the
following bus cycle termination. The pre- and post-data cycles are not included in
the data duration.
3-4
Conexant
100660E