CN8478 Datasheet, PDF (49/221 Pages) Conexant Systems, Inc – Multichannel Synchronous Communications Controller (MUSYCC)

CN8478/CN8474A/CN8472A/CN8471A
Multichannel Synchronous Communications Controller (MUSYCC™)
2.0 Host Interface
2.2 PCI Configuration Registers
Register 3, Address 0Ch
Table 2-6. Register 3, Address 0Ch
Bit
Field
Name
Reset
Value
Type
Description
31
Built-In Self Test (BIST)
1
Capable
RO Returns 1 if device supports BIST. Returns 0 if it does not
support BIST.
30
Start BIST
0
RW Writes 1 to invoke BIST. Device resets the bit when BIST is
complete. Software should fail the device if BIST is not complete
after two seconds.
29:27 Reserved
0
RO Unused.
26
BIST Error in the
Interrupt Queue
—
RO After “Start BIST” bit gets reset, this bit indicates if there were
any errors in the interrupt queue RAM areas.
25
BIST Error in the
Transmitter
—
RO After “Start BIST” bit gets reset, this bit indicates if there were
any errors in the transmit queue RAM areas.
24
BIST Error in the
Receiver
—
RO After “Start BIST” bit gets reset, this bit indicates if there were
any errors in the receive queue RAM areas.
23:16 Header Type
80h
RO MUSYCC is a multifunction device with the standard layout of
configuration register space.
15:11
10:8
Latency Timer
0
RW The latency timer is an 8-bit value that specifies the maximum
number of PCI clock cycles that MUSYCC can keep the bus after
0
RO
starting the access cycle by asserting its FRAME*. The latency
timer ensures that MUSYCC has a minimum time slot for it to
own the bus, but places an upper limit on how long it will own
the bus.
7:0 Reserved
0
RO Unused.
NOTE(S): An active-low signal is denoted by a trailing asterisk (*).
100660E
Conexant
2-11