CN8478 Datasheet, PDF (67/221 Pages) Conexant Systems, Inc – Multichannel Synchronous Communications Controller (MUSYCC)

CN8478/CN8474A/CN8472A/CN8471A
Multichannel Synchronous Communications Controller (MUSYCC™)
3.0 Expansion Bus (EBUS)
3.1 Operation
Table 3-2 shows the effective signals when Motorola-style protocol is
selected.
Table 3-2. Motorola Protocol Signal
Signal
Description
Interpretation
AS*
Address Strobe
Driven low by MUSYCC to indicate that the address
lines contain a valid address. This signal remains
asserted for the duration of the access cycle.
DS*
Data Strobe
Strobed low by MUSYCC to enable data reads or data
writes for the addressed device.
R/WR*
Read/Write
Held high throughout read operation and held low
throughout write operation by MUSYCC. This signal
determines the meaning (read or write) of DS*.
BR*
Bus Request
Asserted low by MUSYCC when it requests the EBUS
from a bus arbiter.
BG*
Bus Grant
Asserted low by bus arbiter in response to BR* signal
assertion. Remains asserted until after the BR* signal
is deasserted. If the EBUS is connected and there are
no bus arbiters on the EBUS, this signal must be
asserted low at all times.
BGACK*
Bus Grant
Acknowledge
Asserted low by MUSYCC when it detects BGACK*
currently deasserted. As this signal is asserted,
MUSYCC begins the EBUS access cycle. After the
cycle is finished, this signal is deasserted indicating to
the bus arbiter that MUSYCC has released the EBUS.
NOTE(S): An active low signal is denoted by a trailing asterisk (*).
3.1.10 Arbitration
The HOLD and HLDA (Intel style) or BR* and BG* (Motorola style) signal lines
are used by MUSYCC to arbitrate for the EBUS.
For Intel-style interfaces, the arbitration protocol is as follows (refer to
Figure 7-13, EBUS Write/Read Transactions, Intel-Style):
1. MUSYCC three-states EAD[31:0], EBE*[3:0]. WR*, RD*, and ALE*.
2. MUSYCC requires EBUS access and asserts HOLD.
3. MUSYCC checks for HLDA assertion by bus arbiter.
4. If HLDA is deasserted, MUSYCC waits for the HLDA signal to become
asserted before continuing the EBUS operation.
5. If HLDA is asserted, MUSYCC continues with the EBUS access because
it has control of the EBUS.
6. MUSYCC drives EAD[31:0], EBE*[3:0], WR*, RD*, and ALE*.
7. MUSYCC completes EBUS access and deasserts HOLD.
8. Bus arbiter deasserts HLDA shortly thereafter.
9. MUSYCC three-states EAD[31:0], EBE*[3:0]. WR*, RD*, and ALE*.
100660E
Conexant
3-7