CN8478 Datasheet, PDF (75/221 Pages) Conexant Systems, Inc – Multichannel Synchronous Communications Controller (MUSYCC)

CN8478/CN8474A/CN8472A/CN8471A
Multichannel Synchronous Communications Controller (MUSYCC™)
4.0 Serial Interface
4.5 Channelized Port Mode
Figure 4-2. Transmit and Receive T1 Mode
RCLK
RSYNC-RISE(a)
RDATA-RISE(a)
6
7 F-bit 0
1
2
3
4
5
6
7
0
RSYNC-RISE(b)
RDAT-FALL(b)
6
7 F-bit 0
1
2
3
4
5
6
7
0
RSYNC-FALL(c)
RDATA-RISE(c)
6
7 F-bit 0
1
2
3
4
5
6
7
0
RSYNC-FALL(d)
RDAT-FALL(d)
6
7 F-bit 0
1
2
3
4
5
6
7
0
TCLK
TSYNC-RISE(a)
TDAT-RISE(a)
TSYNC-RISE(b)
TDATA-FALL(b)
TSYNC-FALL(c)
TDAT-RISE(c)
TSYNC-FALL(d)
TDATA-FALL(d)
8478_014
6
7 F-bit 0
1
2
3
4
5
6
7
0
6
7 F-bit 0
1
2
3
4
5
6
7
0
6
7 F-bit 0
1
2
3
4
5
6
7
0
6
7 F-bit 0
1
2
3
4
5
6
7
0
NOTE(S):
1. T1 Mode employs 24 time slots (0–23) with 8 bits per time slot (0–7) and 1 frame bit every 193 clock periods. One frame
of 193 bits occurs every 125 µs—1.544 MHz.
2. RSYNC and TSYNC must be asserted for a minimum of 1 CLK period.
3. MUSYCC can be configured to sample RSYNC, TSYNC, RDAT, and TDAT on either a rising or falling clock edge
independent of any other signal sampling configuration.
4. Relationships between the various configurations of active edges for the synchronization signal and the data signal are
shown using a common clock signal for receive and transmit operations. Note the relationship between the frame bit
(within RDAT, TDAT) and the frame synchronization signal (e.g., RSYNC, TSYNC).
5. All received signals (e.g., RSYNC, RDAT, TSYNC) are sampled on the specified clock edge (e.g., RCLK, TCLK). All transmit
data signals (TDAT) are latched on the specified clock edge.
6. In configuration (a), synchronization and data signals are sampled or latched on a rising clock edge.
7. In configuration (b), synchronization signal is sampled on a rising clock edge, and the data signal is sampled or latched on
a falling clock edge.
8. In configuration (c), synchronization signal is sampled on a falling clock edge, and the data signal is sampled or latched on
a rising clock edge.
9. In configuration (d), synchronization and data signals are sampled or latched on a falling clock edge.
100660E
Conexant
4-5