CN8478 Datasheet, PDF (190/221 Pages) Conexant Systems, Inc – Multichannel Synchronous Communications Controller (MUSYCC)

7.0 Electrical and Mechanical Specifications
CN8478/CN8474A/CN8472A/CN8471A
7.2 Timing and Switching Specifications
Multichannel Synchronous Communications Controller (MUSYCC™)
Table 7-4. PCI Interface DC Specifications (2 of 2)
Symbol
Parameter
Condition
Min
Max
Unit
V_ol
C_in
C_clk
C_IDSEL
L_pin
Output Low Voltage⁽³⁾
Input Pin Capacitance⁽⁴⁾
CLK Pin Capacitance
IDSEL Pin Capacitance⁽⁵⁾
Pin Inductance⁽⁶⁾
I_out = 1500 µA
—
0.1 V_DD
V
—
—
10
pF
—
5
12
pF
—
—
8
pF
—
—
20
nH
NOTE(S):
(1) _{Guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to pull a floated network.}
Applications sensitive to static power utilization should ensure that the input buffer is conducting minimum current at this
input voltage.
(2) _{Input leakage currents include hi-Z output leakage for all bidirectional buffers with three-state outputs.}
(3) _{Signals without pull-up resistors must have 3 mA low output current. Signals requiring pull-up must have 6 mA; the latter}
includes FRAME*, TRDY*, IRDY*, DEVSEL*, STPP*, SERR*, and PERR*
(4) _{Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK) with an exception granted to motherboard-only}
devices, which could be up to 16 pF, in order to accommodate PGA packaging. This would mean, in general, that components
for expansion boards would need to use alternatives to ceramic PGA packaging – i.e., PQFP, SGA, etc.
(5) _{Lower capacitance on this input-only pin allows for non-resistive coupling to AD[xx].}
(6) _{This is a recommendation, not an absolute requirement. The actual value should be provided with the component data sheet.}
Table 7-5. PCI Clock (PCLK) Waveform Parameters, 33 MHz PCI Clock
Symbol
Parameter
Min
Max
Unit
T_cyc
Clock Cycle Time⁽¹⁾
30
—
ns
T_high
Clock High Time
11
—
ns
T_low
Clock Low Time
11
—
ns
–
Clock Slew Rate⁽²⁾
1
4
V/ns
V_ptp
Peak-to-Peak Voltage
0.4 V_dd
—
V
NOTE(S):
(1) _{MUSYCC works with any clock frequency between DC and 66 MHz, nominally. The clock frequency can be changed at any}
time during operation of the system as long as clock edges remain monotonic, and minimum cycle and high and low times
are not violated. The clock can only be stopped in a low state.
(2) _{Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum}
peak-to-peak portion of the clock waveform.
7-4
Conexant
100660E