CN8478 Datasheet, PDF (77/221 Pages) Conexant Systems, Inc – Multichannel Synchronous Communications Controller (MUSYCC)

CN8478/CN8474A/CN8472A/CN8471A
Multichannel Synchronous Communications Controller (MUSYCC™)
4.0 Serial Interface
4.5 Channelized Port Mode
Figure 4-4. Transmit and Receive Nx64 Mode
RCLK
RSYNC-RISE(a)
RDATA-RISE(a)
RSYNC-RISE(b)
RDAT-FALL(b)
6
7
0
1
2
3
4
5
6
7
0
1
6
7
0
1
2
3
4
5
6
7
0
1
RSYNC-FALL(c)
RDATA-RISE(c)
RSYNC-FALL(d)
RDAT-FALL(d)
6
7
0
1
2
3
4
5
6
7
0
1
6
7
0
1
2
3
4
5
6
7
0
1
TCLK
TSYNC-RISE(a)
TDAT-RISE(a)
TSYNC-RISE(b)
TDATA-FALL(b)
TSYNC-FALL(c)
TDAT-RISE(c)
TSYNC-FALL(d)
TDATA-FALL(d)
8478_016
2
3
4
5
6
7
0
1
2
3
4
5
2
3
4
5
6
7
0
1
2
3
4
5
2
3
4
5
6
7
0
1
2
3
4
5
2
3
4
5
6
7
0
1
2
3
4
5
NOTE(S):
1. Nx64 Mode employs N time slots with 8 bits (0–7) per time slot.
2. RSYNC and TSYNC must be asserted for a minimum of 1 CLK period.
3. Assertion of TSYNC must precede transmission of bit 0 of a frame by exactly 4 line clock periods due to the internal buffer
scheme used for transmitting of Nx64 mode data bits.
4. RSYNC and TSYNC signals must be provided for every received and transmitted frame in Nx64 mode.
5. If N = 1, the minimum, then 8 bits/frame = 64 kHz. If N = 128, the maximum, then 1024 bits/frame = 8.192 MHz.
6. Relationships between the various configurations of active edges for the synchronization signal and the data signal are
shown using a common clock signal for receive and transmit operations. Note the relationship between the frame bit
(within RDAT, TDAT) and the frame synchronization signal (e.g., RSYNC, TSYNC).
7. All received signals (e.g., RSYNC, RDAT, TSYNC) are sampled on the specified clock edge (e.g., RCLK, TCLK). All transmit
data signals (TDAT) are latched on the specified clock edge.
8. In configuration (a), synchronization and data signals are sampled or latched on a rising clock edge.
9. In configuration (b), synchronization signal is sampled on a rising clock edge, and the data signal is sampled or latched on
a falling clock edge.
10. In configuration (c), synchronization signal is sampled on a falling clock edge, and the data signal is sampled or latched on
a rising clock edge.
11. In configuration (d), synchronization and data signals are sampled or latched on a falling clock edge.
100660E
Conexant
4-7