CN8478 Datasheet, PDF (58/221 Pages) Conexant Systems, Inc – Multichannel Synchronous Communications Controller (MUSYCC)

2.0 Host Interface
2.2 PCI Configuration Registers
CN8478/CN8474A/CN8472A/CN8471A
Multichannel Synchronous Communications Controller (MUSYCC™)
The longest latency MUSYCC experiences in gaining access to the PCI bus is
k–1
Ã¥ ^{LatencyTotal =}
(T_i + 8)
i=0
or [k x (T + 8)] when all T_is are equal, where:
k = the number of PCI masters in the system
T = the value of the latency timers in those masters
8 = the longest target latency allowed, in clock cycles (exception: the first data
phase is allowed 16 clock cycles)
Once a master gets the bus, it starts a count-down timer loaded with the
value T, from the latency timer register. When the count reaches 0, the master
relinquishes the bus when its GNT* is removed and it sees TRDY* on the final
data phase. As long as its GNT* is still asserted, the master is free to burst
indefinitely. Table 2-17 provides an example of PCI latency.
Table 2-17. PCI Latency Example
PCI Clock Increment
Bus Activity
0
Bus is idle.
Host asserts REQ*.
MUSYCC asserts REQ*.
+1
Host gets GNT*.
These 2 clock cycles are the arbitration latency
that becomes 0 if the bus was not idle.
+1
Host asserts FRAME* to start access cycle.
+(T + 8) or [16 + (n - 1) x 8] This is the bus acquisition latency time—the amount of time the next requestor must wait for the
whichever is smaller
bus because of current master, the host.
— Host has bus —
During this time, assume the host loses its GNT* just +1 clock cycle into its acquisition and
MUSYCC0 receives the GNT* +1 into this time.
The host’s first data phase must finish within 16 PCI clock cycles, and subsequent data phases
must finish within 8 cycles each. Therefore, 16 + (n - 1) x 8 clock cycles is how long the host will
need the bus to execute n data phases (n dword burst), assuming the host’s access finishes before
its latency timer expires.
As the cycle finishes, the host relinquishes the bus, and one clock cycle later, MUSYCC0 gets
the GNT* and subsequently asserts its FRAME* to start the access cycle.
+(T + 8) or [16 + (n - 1) x 8] MUSYCC0 finishes with the bus, and MUSYCC1 has it on the next clock cycle. During this time,
whichever is smaller
MUSYCC0 loses its GNT*, and MUSYCC1 receives its GNT*. MUSYCC0 behaves similarly to the
— MUSYCC0 has bus —
host above.
+(T + 8) or [16 + (n - 1) x 8]
whichever is smaller
— MUSYCC1 has bus —
MUSYCC1 finishes with the bus, and MUSYCC2 has it on the next clock cycle. During this time,
MUSYCC1 loses its GNT*, and MUSYCC2 receives its GNT*. MUSYCC1 behaves similarly to the
host above.
NOTE(S): An active low signal is denoted by a trailing asterisk (*).
2-20
Conexant
100660E