CN8478 Datasheet, PDF (112/221 Pages) Conexant Systems, Inc – Multichannel Synchronous Communications Controller (MUSYCC)

5.0 Memory Organization
5.2 Descriptors
CN8478/CN8474A/CN8472A/CN8471A
Multichannel Synchronous Communications Controller (MUSYCC™)
Accessing the Time Slot Map or Subchannel Map within MUSYCC requires
that a serial line clock be present at the serial interface. If a clock is not present,
writes are ignored, and reads return all 1s.
The host can read and write the Receive Time Slot Map from within
MUSYCC; however the host can only write the Transmit Time Slot Map into
MUSYCC. The transmit maps are stored in write-only registers. Reading transmit
maps results in all 1s being returned.
The host can read and write the Receive Subchannel Map from within
MUSYCC; however, the host can only write the Transmit Subchannel Map into
MUSYCC. The transmit maps are stored in write-only registers. Reading the
transmit map results in all 1s being returned.
5.2.3 Channel Level Descriptors
The channel level descriptors contain information necessary to configure channel
registers.
5.2.3.1 Channel
Configuration Descriptor
The Channel Configuration Descriptor configures aspects of the channel
common to all messages passing through the channel. One descriptor exists for
each logical channel direction.
Table 5-18 lists the values and description of each channel configuration
descriptor.
Table 5-18. Channel Configuration Descriptor (1 of 3)
Bit
Field
Name
Value
Description
31
PADJ
30
29:24
RSVD
BUFFLOC[5:0]
23
INV
22
21:16
RSVD
BUFFLEN[5:0]
15
EOPI
0
1
0
00h–3Fh
0
0
00h–3Fh
0
1
Pad Count Adjustment disabled. No adjustment is made to the value of
PADCNT if Zero Insertions is detected.
Pad Count Adjustment enabled. The value of PADCNT is reduced if Zero
Insertions is detected. This adjustment is required for rate adaptive applications
such as ITU-T Recommendation V.120.
Reserved
Channel Buffer Location Index. Starting location of internal FIFO data buffer for
this channel and direction.
Data Inversion disabled. All data bits in message are not inverted between
shared memory and MUSYCC.
Reserved.
Internal Data Buffer Length. Number of internal FIFO data buffer locations
allocated to this channel and direction equals 2 x (BUFFLEN+1) dwords.
End Of Padfill Interrupt disabled. Transmit Only. After outputting last padfill
code, do not generate interrupt indicating condition.
End of Padfill Interrupt enabled.
5-26
Conexant
100660E