CN8478 Datasheet, PDF (85/221 Pages) Conexant Systems, Inc – Multichannel Synchronous Communications Controller (MUSYCC)

CN8478/CN8474A/CN8472A/CN8471A
4.0 Serial Interface
Multichannel Synchronous Communications Controller (MUSYCC™) 4.7 Tx and Rx FIFO Buffer Allocation and Manage-
4.7.2 Receiving Bit Stream
As a receive channel is activated, MUSYCC reads in descriptors from shared
memory and prepares Rx-BLP and Rx-DMAC to service incoming serial data
accordingly, assuming all configurations are proper, and incoming data can be
written to shared memory.
Upon channel activation, the receiver starts storing received data into a
BUFFLEN+1 size of FIFO, starting at BUFFLOC offset in the FIFO buffer area.
As this buffer fills, the BLP instructs the DMAC to start a PCI data transfer cycle
to shared memory of the FIFO buffer contents and simultaneously starts filling
another BUFFLEN+1 size of FIFO buffer from the serial port. Generally, half the
FIFO buffer space for a channel is used for serial port data reception, and half for
shared memory data transfers.
The DMAC-initiated PCI transfer cycle requires MUSYCC to arbitrate for the
PCI bus, initiate a master write to shared memory over the PCI bus, and conclude
the transfer by releasing the PCI bus. MUSYCC transfers data autonomously and
always attempts to burst data to the PCI.
4.7.3 Transmitting Bit Stream
When a transmit channel is activated, MUSYCC reads in descriptors from shared
memory and prepares Tx-BLP and Tx-DMAC to service outgoing serial data,
assuming all configurations are proper, and outgoing data can be read from
shared memory.
Upon channel activation, the transmitter initiates a PCI data transfer cycle
from shared memory of data to be output to the serial port. As the DMAC
receives data over the PCI, it forwards it to the BLP which fills a BUFFLEN+1
size of FIFO starting at BUFFLOC offset in the FIFO area. Generally, half the
FIFO space for a channel is used for serial port data transmission and half for
shared memory data transfers.
The DMAC-initiated PCI transfer cycle requires that MUSYCC arbitrate for
the PCI bus, initiate a master read from shared memory over the PCI bus, and
conclude the transfer by releasing the PCI bus. MUSYCC transfers data
autonomously and always attempts to burst data from the PCI.
100660E
Conexant
4-15