CN8478 Datasheet, PDF (184/221 Pages) Conexant Systems, Inc – Multichannel Synchronous Communications Controller (MUSYCC)

6.0 Basic Operation
6.5 Signaling System 7
CN8478/CN8474A/CN8472A/CN8471A
Multichannel Synchronous Communications Controller (MUSYCC™)
6.5.3 Signal Unit Error Rate Monitoring
The Signal Unit Error Rate Monitor (SUERM) facility provides a 6-bit counter
which serves as a real-time figure-of-merit for the receive link integrity. It is
incremented and decremented in a “leaky-bucket” style, based upon integration
of good message and bad octet periods on the receive channel.
6.5.4 SUERM Counter Incrementing
The SUERM counter increments when any signal unit error occurs. A signal unit
error is defined as one of the following events:
• SHT: Short Frame error
• ALIGN: Octet Alignment error
• CRC: FCS Mismatch error
• Accumulation of 16 octet count errors
Short Frame errors, Octet Alignment errors, or CRC/FCS Mismatch errors
generate a maskable interrupt, SHT, LNG, CRC respectively, toward the host and
cause the SUERM counter to be incremented. Each time the SUERM counter is
incremented, the maskable interrupt SINC is generated to the host indicating this
condition.
6.5.5 SUERM Octet Counting
Octet counting mode is entered if seven consecutive 1s are detected (abort
condition), or the received message length exceeds the selected maximum
received-frame length register value (long frame error)
When in Octet counting mode, a 4-bit bad octet counter is incremented for
every received octet until a condition is met to exit this mode. As the counter rolls
over from 15 to 0, the SUERM counter is incremented by one. This mode is
exited when a correctly checked signal unit (unerrored message) is detected.
Each time the octet counting mode is entered, the value of 4-bit bad octet
counter is reset.
6.5.6 SUERM Counter Decrementing
The SUERM counter is decremented when 256 unerrored messages are received.
An unerrored message indicates that a short frame or long frame error was not
detected, no octet alignment error was detected, and no CRC error was detected.
Each unerrored message increments an 8-bit good message counter. When this
counter rolls over from 255 to 0, the SUERM counter is decremented by one.
While in octet counting mode, the value of the 8-bit good message counter is
maintained from the last non-octet counting mode and starts to increment again
from that value when a good message causes an exit from the octet counting
mode.
When the SUERM counter decrements, the maskable interrupt SDEC is
generated to the host indicating this condition.
6-50
Conexant
100660E