CN8478 Datasheet, PDF (63/221 Pages) Conexant Systems, Inc – Multichannel Synchronous Communications Controller (MUSYCC)

CN8478/CN8474A/CN8472A/CN8471A
Multichannel Synchronous Communications Controller (MUSYCC™)
3.0 Expansion Bus (EBUS)
3.1 Operation
The EBUS interface transfers 32 bits of the data lines between the EBUS and
the PCI bus. The byte-enable signal lines EBE[3:0]* are transferred from the PCI
byte-enable signal lines CBE[3:0]* to the EBUS, and indicate which byte(s) in the
data dword are valid. Figure 3-3 illustrates both data and data configurations of
the 32-bit word.
Figure 3-3. EBUS Address/Data Line Structure
Address Lines–EAD[31:0] During Address Phase
31
20 19 17
00000000000000
00 YYYYYYYYYYYYYYYYYY
0 Bit Number
Upper 12 Bits
always 0 during
address phase
Lower 20 Bits
AD[19:2] transferred from PCI Bus
to EAD[17:0] on the EBUS.
Byte addressing with bits 19 and 18
always 0 during address phase.
Data Lines–EAD[31:0] During Data Phase
31
YYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYY
All 32 bits transferred between PCI bus and EBUS.
The byte enable lines indicate which bits are valid in
the 32-bit dword during the data phase.
0 Bit Number
8478_009
NOTE(S):
1. Byte Enable 0–EBE[0]* signals if EAD[7:0] are valid data bits during data phase.
2. Byte Enable 1–EBE[1]* signals if EAD[15:8] are valid data bits during data phase.
3. Byte Enable 2–EBE[2]* signals if EAD[23:16] are valid data bits during data phase.
4. Byte Enable 3–EBE[3]* signals if EAD[31:24] are valid data bits during data phase.
5. An active low signal is denoted by a trailing asterisk (*).
3.1.3 Clock
The ECLK is derived from the PCI clock and runs at up to a 33 MHz clock rate.
This operation is controlled by the M66EN input on Revision C and later devices.
An asserted M66EN input implies that the overall system is operating at a 66
MHz PCI clock rate; the ECLK is running at half of the PCI clock rate.
Otherwise, the ELCK is operating at the same rate as the PCI clock frequency. In
order to ensure that the ELCK is properly operational, the M66EN input state
shall not be changed during the whole operational period.
The EBUS clock output can be disabled by setting the ECKEN bit field (see
Table 5-6). In the disabled state, the ECLK output is three-stated.
100660E
Conexant
3-3