CN8478 Datasheet, PDF (72/221 Pages) Conexant Systems, Inc – Multichannel Synchronous Communications Controller (MUSYCC)

4.0 Serial Interface
4.1 Serial Port Interface
CN8478/CN8474A/CN8472A/CN8471A
Multichannel Synchronous Communications Controller (MUSYCC™)
4.1 Serial Port Interface
A receive serial port interface (Rx-SERI) connects to four input signals: RCLK,
RDAT, RSYNC, and ROOF. A transmit serial port interface (Tx-SERI) connects
to two input signals and one output signal, TCLK, TSYNC, and TDAT,
respectively (refer to Table 1-4, CN8478 Hardware Signal Definitions). The SERI
is responsible for receiving and transmitting data bits to FIFO buffers in the BLP.
The receive and transmit data and synchronization signals are synchronous to
the receive and transmit line clocks, respectively. MUSYCC can be configured to
sample in and latch out data signals and sample in status and synchronization
signals on either the rising or falling edges of the respective line clock, RCLK and
TCLK. This configuration is accomplished by setting the ROOF_EDGE,
RSYNC_EDGE, RDAT_EDGE, TSYNC_EDGE, and TDAT_EDGE bit fields
(detailed in Table 5-12, Port Configuration Descriptor).
The default, after device reset, is to sample in and latch out data,
synchronization, and status on the falling edges of the respective line clock.
4.2 Bit Level Processor
The bit-level processors (Rx-BLP and Tx-BLP) service the bits in the receive and
transmit path. As internal FIFO buffers are filled and flushed, the BLP requests
memory transfers from the DMAC. The BLP coordinates all bit-level transactions
between SERI and DMAC. The BLP also interacts with the INTC to notify the
host of events and errors during bit-level processing.
4.3 DMA Controller
The DMA controllers (Rx-DMAC and Tx-DMAC) manage all memory
operations between a corresponding BLP and the host interface. DMAC takes
requests from BLP to either fill or flush internal FIFO buffers, sets up an access
to data buffers in shared memory, and requests access to the PCI bus through the
host interface.
4.4 Interrupt Controller
The interrupt controller takes receive and transmit events from Rx-BLP and
Tx-BLP, respectively. The INTC coordinates the transfer of internally queued
descriptors to an interrupt queue in shared memory and also coordinates the
notification to the host of pending interrupts.
4-2
Conexant
100660E