CN8478 Datasheet, PDF (91/221 Pages) Conexant Systems, Inc – Multichannel Synchronous Communications Controller (MUSYCC)

CN8478/CN8474A/CN8472A/CN8471A
Multichannel Synchronous Communications Controller (MUSYCC™)
5.0 Memory Organization
5.1 Memory Architecture
The first four registers in each group (shown in bold-type in Table 5-1) are
located exclusively within MUSYCC. These registers are accessed by the host
using direct reads and writes to the corresponding register map address. The
remaining registers have corresponding locations within shared memory, and the
host accesses the shared memory image rather than the internal registers.
Regardless, the values within MUSYCC are always the values used during device
operation. After configuring the shared memory image of these registers, the host
issues a service request by writing directly into the Service Request Descriptor.
This causes MUSYCC to copy the image from shared memory.
Each supported channel group requires its own group structure to operate. The
Dual Address Cycle Base Pointer, Interrupt Status Descriptor, Global
Configuration Descriptor, and the Interrupt Queue Descriptor are common
among all supported groups.
The Transmit Time Slot Map and the Transmit Subchannel Map are
write-only areas within MUSYCC; reading from these areas results in all 1s being
returned.
The Service Request Descriptors are locations within MUSYCC where
commands can be directed to individual channel groups. The host writes a service
request (a command) directly into the corresponding group’s register. MUSYCC
behaves as a PCI slave as this write is performed. The action resulting from the
command may cause MUSYCC to read or write locations from shared memory.
While MUSYCC accesses shared memory, it behaves as a PCI master and
arbitrates for control of the bus autonomously.
MUSYCC’s registers can be initialized before or after shared memory resident
descriptors are initialized. The recommended sequence is to configure shared
memory descriptors first, then copy the relevant information to MUSYCC’s
registers via the service request mechanism.
NOTE: Upon channel activation, shared memory and internal registers must be
initialized, valid, and available to MUSYCC. MUSYCC uses the
information within the shared memory descriptors to transfer data between
the serial interface and shared memory. MUSYCC assumes the
information is valid once a channel is activated.
100660E
Conexant
5-5