CN8478 Datasheet, PDF (102/221 Pages) Conexant Systems, Inc – Multichannel Synchronous Communications Controller (MUSYCC)

5.0 Memory Organization
5.2 Descriptors
CN8478/CN8474A/CN8472A/CN8471A
Multichannel Synchronous Communications Controller (MUSYCC™)
5.2.2.3 Group The Group Configuration Descriptor contains configuration bits applying to all
Configuration Descriptor 32 logical channels within a given channel group as listed in Table 5-10.
Table 5-10. Group Configuration Descriptor (1 of 2)
Bit
Field
Name
Value
Description
31:22
21:16
15
RSVD
SUET[5:0]
SFALIGN
14:12
11:10
RSVD
POLLTH[1:0]
9
INHTBSD
8
INHRBSD
7
MEMPVA
0
Reserved.
Signal Unit Error Threshold. Sets maximum value of SUERM counter. When SUERM
exceeds this count, a SUERR interrupt is generated.
0
Super Frame Alignment. Flywheel Mechanism. Select roll over to 0 of time slot counter
(the flywheel mechanism in the serial interface) as a frame synchronization event.
For a transparent mode channel, wait for the flywheel to roll over to start message
processing after channel activation.
For descriptor polling, use the flywheel roll-over as a frame synchronization event.
The polling frequency is determined by using the poll-throttle field elsewhere in this
descriptor.
1
Super Frame Alignment. External Signal. Select detection of frame synchronization
signal (TSYNC or RSYNC) assertion as frame synchronization event.
For a transparent mode channel, wait for assertion of signal to start message
processing after channel activation.
For descriptor polling, use assertion of signal as frame synchronization event.
Polling frequency is determined by using poll-throttle field elsewhere in this descriptor.
0
Reserved.
0
Poll Throttle. Poll at every frame synchronization event. Not supported.
1
Poll at every 16^th frame synchronization event.
2
Poll at every 32^nd frame synchronization event.
3
Poll at every 64^th frame synchronization event.
0
Inhibit Transmit Buffer Status Descriptor Disabled. At end of each transmitted data
buffer, do not inhibit (allow) overwriting of Tx Buffer Descriptor with a Tx Buffer Status
Descriptor.
1
Inhibit Transmit Buffer Status Descriptor. As the Tx Buffer Status Descriptor is being
inhibited, the host must rely on an interrupt for status information regarding
transmitted data message.
0
Inhibit Receive Buffer Status Descriptor Disabled. At the end of each Receive Data
Buffer, do not inhibit (allow) overwriting of Rx Buffer Descriptor with a Rx Buffer
Status Descriptor.
1
Inhibit Receive Buffer Status Descriptor. As the Rx Buffer Status Descriptor is being
inhibited, the host must rely on an interrupt for status information regarding the
received data message.
0
Memory Protection Violation Action. Reset Group. On a memory protection violation
error, group reset is performed. As a result, all 32 channels are deactivated in both
receive and transmit directions.
1
Memory Protection Violation Action. Deactivate Channel. On a memory protection
violation error, only the channel being serviced during violation is deactivated in both
receive and transmit directions.
5-16
Conexant
100660E