CN8478 Datasheet, PDF (90/221 Pages) Conexant Systems, Inc – Multichannel Synchronous Communications Controller (MUSYCC)

5.0 Memory Organization
5.1 Memory Architecture
CN8478/CN8474A/CN8472A/CN8471A
Multichannel Synchronous Communications Controller (MUSYCC™)
The 1 MB memory ranges assigned to MUSYCC functions will not restrict
MUSYCC’s PCI interface from attempting to access these ranges. The host must
be cognizant that MUSYCC cannot respond to an access cycle which MUSYCC
itself initiates as the bus master.
Table 5-1. MUSYCC Register Map
Register Map
Group
(Byte Offset from Base Address Register)
0
1
2
3
4
5
6
7
Group Base Pointer
0000h 0800h 1000h 1800h 2000h 2800h 3000h 3800h
Dual Address Cycle Base Pointer⁽¹⁾
00004h
Service Request Descriptor
0008h 0808h 1008h 1808h 2008h 2808h 3008h 3808h
Interrupt Status Descriptor⁽¹⁾
000Ch
Transmit Time Slot Map⁽²⁾
0200h 0A00h 1200h 1A00h 2200h 2A00h 3200h 3A00h
Transmit Subchannel Map⁽²⁾
0280h 0A80h 1280h 1A80h 2280h 2A80h 3280h 3A80h
Transmit Channel Configuration
Table⁽²⁾
0380h 0B80h 1380h 1B80h 2380h 2B80h 3380h 3B80h
Receive Time Slot Map⁽²⁾
0400h 0C00h 1400h 1C00h 2400h 2C00h 3400h 3C00h
Receive Subchannel Map⁽²⁾
0480h 0C80h 1480h 1C80h 2480h 2C80h 3480h 3C80h
Receive Channel Configuration
Table⁽²⁾
0580h 0D80h 1580h 1D80h 2580h 2D80h 3580h 3D80h
Global Configuration Descriptor⁽¹⁾
00600h
Interrupt Queue Descriptor⁽¹⁾
00604h
Group Configuration Descriptor
060Ch 0E0Ch 160Ch 1E0Ch 260Ch 2E0Ch 360Ch 3E0Ch
Memory Protection Descriptor
0610h 0E10h 1610h 1E10h 2610h 2E10h 3610h 3E10h
Message Length Descriptor
0614h 0E14h 1614h 1E14h 2614h 2E14h 3614h 3E14h
Port Configuration Descriptor
0618h 0E18h 1618h 1E18h 2618h 2E18h 3618h 3E18h
Receive BIST Status⁽³⁾
00640h
Transmit BIST Status⁽³⁾
00644h
NOTE(S):
(1) _{MUSYCC automatically maps Group 1 through 7 addresses for these registers to the Group 0 address (shown). For example,}
accessing address 00E00h in MUSYCC (address for Group 1 Global Configuration register) automatically maps to address
00600h and the contents of 00600h is read or written.
(2) _{The following descriptors are mapped to Internal RAM: Transmit Time Slot Map, Transmit Subchannel Map, Transmit}
Channel Configuration Table, Receive Time Slot Map, Receive Subchannel Map, and Receive Configuration Table. Host must
not access internal RAM while channels are active. Updates to RAM must be performed via a service request.
(3) _{The receive/transmit BIST diagnostic status registers.}
5-4
Conexant
100660E