CN8478 Datasheet, PDF (51/221 Pages) Conexant Systems, Inc – Multichannel Synchronous Communications Controller (MUSYCC)

CN8478/CN8474A/CN8472A/CN8471A
Multichannel Synchronous Communications Controller (MUSYCC™)
2.0 Host Interface
2.2 PCI Configuration Registers
Register 15, Address 3Ch
Table 2-9. Register 15, Address 3Ch
Bit
Field
Name
Reset
Value
Type
Description
31:24 Maximum Latency
0Fh
RO Specifies how quickly MUSYCC needs to gain access to the PCI
bus. The value is specified in 0.25 µs increments and assumes a
33 MHz clock. 0Fh means MUSYCC needs to gain access to the
PCI bus every 130 PCI clock cycles, expressed as 3.75 µs in this
register for 33 MHz PCI and 1.87 µs for 66 MHz PCI.
23:16 Minimum Grant
0
RO
This value specifies, in 0.25 µs increments, the minimum burst
period MUSYCC needs. MUSYCC does not have any special
MIN_GNT requirements. In general, the more channels MUSYCC
has active, the worse the bus latency and the shorter the burst
cycle.
15:8 Interrupt Pin
01b
RO Defines which PCI interrupt pin Function 0 uses. 01h means
MUSYCC uses pin INTA* for HDLC controller interrupts.
7:0 Interrupt Line
0
RW Communicates interrupt line routing. System initialization
software will write a value to this register indicating which host
interrupt controller input is connected to MUSYCC’s INTA* pin.
NOTE(S): An active-low signal is denoted by a trailing asterisk (*).
2.2.2 Function 1 Expansion Bus Bridge, PCI Slave
MUSYCC, a multifunction PCI device, provides the necessary configuration
space allowing a PCI bus or system controller to query and configure the host
interface of MUSYCC as a PCI device. PCI configuration space consists of a
device-independent header region (64 bytes) and a device-dependent header
region (192 bytes). MUSYCC provides the 64-byte device-independent header
section only. Access to the device-dependent header region results in 0s being
read, and no effect on writes.
There are three types of registers available in MUSYCC:
1. Read-Only (RO)—Returns a fixed bit pattern if the register is used, or a 0
if the register is unused or reserved.
2. Read-Resettable (RR)—Can be reset to 0 by writing a 1 to the register.
3. Read/Write (RW)—Retains the value last written to it.
MUSYCC’s Function 1 Configuration Space has 16 dword registers.
Tables 2-10 through 2-16 describe these registers.
100660E
Conexant
2-13