CN8478 Datasheet, PDF (33/221 Pages) Conexant Systems, Inc – Multichannel Synchronous Communications Controller (MUSYCC)

CN8478/CN8474A/CN8472A/CN8471A
Multichannel Synchronous Communications Controller (MUSYCC™)
1.0 System Description
1.1 Pin Descriptions
Table 1-4. CN8478 Hardware Signal Definitions (1 of 6)
MQFP
Pin No.
Pin Label
Signal Name
I/O
Definition
190
144-146,
149-152,
154-155,
158-163,
166-170,
173-174,
176-180,
183-184,
187-189
199, 200,
203, 204
192
193
194
195
196
197
198
ECLK
Expansion Bus Clock t/s O ECLK is an inverted version of the PCI clock applied at the PCLK
input.
EAD[31:0] Expansion Bus
Address and Data
t/s I/O
EAD[31:0] is a multiplexed address/data bus. During the address
phase, pins EAD[17:0] contains meaningful address information.
It is the same address as PCI AD[19:2] for the corresponding
cycle.
Pins EAD[31:18] are driven to 0 during the address phase.
This is because those upper bits are compared, during the PCI
address phase, to the value in the relocatable EBUS Base
Address register to determine if the PCI cycle is in fact
addressing into MUSYCC EBUS space.
During data phase of an EBUS access cycle, the PCI signals
AD[31:0] are transferred to the EBUS signal lines EAD[31:0]
unaltered.
EBE[3:0]* Expansion Bus
Byte Enables
t/s O EBE* contains the same information as the PCI byte enables but
is driven in chip select style protocol used as active-low chip
selects when MUSYCC is connected to more than one byte-wide
device. All PCI accesses with byte lane 0’s byte enable asserted
would go to the byte-wide device connected to EAD[7:0].
Likewise, for byte lanes 1, 2, and 3 and EAD[15:8], EAD[23:16],
and EAD[31:24], respectively.
Only the CBE[3:0]* signals from the PCI data phase
(byte-enable signals and not the command signals from the PCI
address phase) are transferred to the EBE[3:0]* signal lines.
EBE* is held high during all other phases of PCI access cycles.
WR* Write Strobe
(R/WR*)
t/s O High-to-low transition enables write data from MUSYCC into
peripheral device. Rising edge defines write. (In Motorola mode,
R/WR* is held high throughout read operation and held low
throughout write operation. Determines meaning of DS* strobe.)
RD*
(DS*)
Read Strobe
t/s O High-to-low transition enables read data from peripheral into
MUSYCC. Held high throughout write operation. (In Motorola
mode, DS* transitions low for both read and write operations
and is held low throughout the operation.
ALE*
(AS*)
Address Latch Enable t/s O High-to-low transition indicates that EAD[31:0] bus contains
valid address. Remains asserted low through the data phase of
the EBUS access. (In Motorola mode, high-to-low transition
indicates EBUS contains valid address. Remains asserted for the
entire access cycle.)
EINT*
Expansion Bus
Interrupt
I EINT* transfers interrupts from local devices to the PCI INTB*
pin.
HOLD
(BR*)
Hold Request
(Bus Request)
t/s O When asserted, MUSYCC requests control of the EBUS.
HLDA
(BG*)
Hold Acknowledge
(Bus Grant)
I When asserted, MUSYCC has access to the EBUS. It is held
asserted when there are no other masters connected to the bus,
or asserted as a handshake mechanism to control EBUS
arbitration.
BGACK* Bus Grant
Acknowledge
t/s O When asserted, MUSYCC acknowledges to the bus arbiter that
the bus grant signal was detected and a bus cycle will be
sustained by MUSYCC until this signal is deasserted.
100660E
Conexant
1-19