CN8478 Datasheet, PDF (167/221 Pages) Conexant Systems, Inc – Multichannel Synchronous Communications Controller (MUSYCC)

CN8478/CN8474A/CN8472A/CN8471A
Multichannel Synchronous Communications Controller (MUSYCC™)
6.0 Basic Operation
6.4 Protocol Support
6.4.8 HDLC Mode
6.4.8.1 Transmit Events
End of Buffer (EOB]
MUSYCC supports three HDLC modes. The modes are assigned on a
per-channel and direction basis by setting the PROTOCOL bit field within the
Channel Configuration Descriptor. The HDLC modes are as follows:
• SS7-HDLC-16CRC: specific SS7 support, HDLC support, 16-bit CRC.
• HDLC-16CRC: HDLC support, 16-bit CRC.
• HDLC-32CRC: HDLC support, 32-bit CRC.
HDLC support by the transmitter includes the following:
• Generating opening, closing, and shared flags.
• 0-bit insertion after five consecutive 1s are transmitted.
• Generating pad fill between frames and adjust for 0 insertions.
• Generating 16- or 32-bit FCS.
• Generating abort sequences upon data corruption in message.
HDLC support by the receiver includes the following:
• Detection and extraction of opening, closing, and shared flags.
• Detection of shared 0 between successive flags.
• 0-bit extraction after five consecutive 1s are received.
• Detecting changes in pad fill idle codes.
• Checking and extracting 16- or 32-bit FCS.
• Checking frame length.
• Checking for octet alignment.
• Checking for abort sequence reception.
Bit Fields within the Transmit Buffer Descriptor specify inter-message bit
level operations. Specifically, when the EOM bit field is set to 1 within a Message
Descriptor by the host, it signifies that the descriptor represents the last buffer for
the current message being transmitted and the bit fields IC, PADEN, PADCNT,
and REPEAT take effect. These bits are collectively known as Message
Configuration Descriptor.
Additionally, the bit field NP in both the Receive and Transmit Buffer
Descriptors enables a polling scheme in case MUSYCC discovers that it does not
own the (next) Message Descriptor.
Transmit events are informational in nature and do not require channel recovery
actions.
Reason:
• DMAC reached the end of a buffer by servicing a number of octets equal
to the bit field BLEN in the Transmit Buffer Descriptor. The last EOB and
an EOM are coincident and result in two separate events being generated.
Effects:
• Interrupt Descriptor in Interrupt Queue with EVENT = EOB, DIR = 1
(if EOBI = 1 in Transmit Buffer Descriptor).
• BLP and DMAC continue with normal message processing. If the DMAC
does not receive more data from shared memory before the BLP must
output the next data bit, the BLP outputs another octet of idle code.
100660E
Conexant
6-33