CN8478 Datasheet, PDF (31/221 Pages) Conexant Systems, Inc – Multichannel Synchronous Communications Controller (MUSYCC)

CN8478/CN8474A/CN8472A/CN8471A
Multichannel Synchronous Communications Controller (MUSYCC™)
Figure 1-12. CN8478 Logic Diagram
1.0 System Description
1.1 Pin Descriptions
Bus Grant Acknowledge I/O ¹⁹⁸ BGACK*
Hold Acknowledge I ¹⁹⁷ HLDA (BG*)
Hold Request O ¹⁹⁶ HOLD (BR*)
Expansion Bus Interrupt I ¹⁹⁵ EINT*
Address Latch Enable O ¹⁹⁴ ALE* (AS*)
Read Strobe O ¹⁹³ RD* (DS*)
Write Strobe/Read O ¹⁹² WR* (R/WR*)
Out-Of-Frame I ²⁰⁷
Clock I ²⁰⁸
Synchronization I ¹
Data I ²
Out-Of-Frame I ⁷
Clock I ⁸
Synchronization I ⁹
Data I ¹⁰
Out-Of-Frame I ¹⁷
Clock I ¹⁸
Synchronization I ¹⁹
Data I ²⁰
Out-Of-Frame I ²⁵
Clock I ²⁶
Synchronization I ²⁹
Data I ³⁰
Out-Of-Frame I ³
Clock I ⁴
Synchronization I ⁵
Data I ⁶
Out-Of-Frame I ¹¹
Clock I ¹²
Synchronization I ¹⁵
Data I ¹⁶
Out-Of-Frame I ²¹
Clock I ²²
Synchronization I ²³
Data I ²⁴
Out-Of-Frame I ³¹
Clock I ³²
Synchronization I ³³
Data I ³⁴
JTAG Clock I 35
JTAG Reset I ³⁶
JTAG Mode Select I ³⁷
JTAG Data Out O ³⁸
JTAG Data In I 39
ROOF[7]
RCLK[7]
RSYNC[7]
RDAT[7]
ROOF[6]
RCLK[6]
RSYNC[6]
RDAT[6]
ROOF[5]
RCLK[5]
RSYNC[5]
RDAT5]
ROOF[4]
RCLK[4]
RSYNC[4]
RDAT[4]
ROOF[3]
RCLK[3]
RSYNC[3]
RDAT[3]
ROOF[2]
RCLK[2]
RSYNC[2]
RDAT[2]
ROOF[1]
RCLK[1]
RSYNC[1]
RDAT[1]
ROOF[0]
RCLK[0]
RSYNC[0]
RDAT[0]
TCK
TRST*
TMS
TDO
TDI
Clock I ⁴³
Reset I ⁴⁵
Grant I ⁴⁶
Initialization Device Select I 60
Frame I/O 75
Initiator Ready I/O 76
Target Ready I/O ⁷⁹
Device Select I/O 80
Stop I/O 83
Parity Error I/O ⁸⁴
Parity I/O 86
Address and Data Bus I/O ⁽³⁾
M66EN I ⁹⁸
PCLK
PRST*
GNT*
IDSEL
FRAME*
IRDY*
TRDY*
DEVSEL*
STOP*
PERR*
PAR
AD[31:0]
M66EN
8478_004
Expansion Bus
Interface
ECLK ¹⁹⁰
EBE[3:0]* ⁽¹⁾
EAD[31:0] ⁽²⁾
O Clock
O Expansion Bus Byte Enable
I/O Expansion Bus Address/Data
Serial Interface
Receive Serial
Channel Group
7
TCLK[7] ¹⁴⁰
Transmit Serial
Channel Group
7
TSYNC[7]
TDAT[7]
149
138
Receive Serial
Channel Group
6
TCLK[6] ¹³¹
Transmit Serial
Channel Group
6
TSYNC[6]
TDAT[6]
130
129
Receive Serial
Channel Group
5
TCLK[5] ¹²⁵
Transmit Serial
Channel Group
5
TSYNC[5]
TDAT[5]
124
123
Receive Serial
Channel Group
4
TCLK[4] ¹¹⁷
Transmit Serial
Channel Group
4
TSYNC[4]
TDAT[4]
116
115
Receive Serial
Channel Group
3
TCLK[3] ¹⁴³
Transmit Serial
Channel Group
3
TSYNC[3]
TDAT[3]
142
141
Receive Serial
Channel Group
2
TCLK[2] ¹³⁶
Transmit Serial
Channel Group
2
TSYNC[2]
TDAT[2]
135
134
Receive Serial
Channel Group
1
Transmit Serial
Channel Group
1
TCLK[1]
TSYNC[1]
TDAT[1]
128
127
126
Receive Serial
Channel Group
0
TCLK[0] ¹²²
Transmit Serial
Channel Group
0
TSYNC[0]
TDAT[0]
121
120
I Clock
I Synchronization
O Data
I Clock
I Synchronization
O Data
I Clock
I Synchronization
O Data
I Clock
I Synchronization
O Data
I Clock
I Synchronization
O Data
I Clock
I Synchronization
O Data
I Clock
I Synchronization
O Data
I Clock
I Synchronization
O Data
Boundary Scan Scan Chain
Test Signal
Test Access
TM[0] ¹¹⁴
TM[1] ¹¹³
TM[2] ¹¹²
I Scan Enable
I Scan Mode Bit 1
I Scan Mode Bit 2
Host (PCI)
Interface
INTB* ⁴⁰
INTA* ⁴¹
CBE[3:0]* ⁽⁴⁾
REQ* 47
SERR* 85
O PCI Interrupt B
O PCI Interrupt A
O Command and Byte Enables
O Request
O System Error
NOTE(S):
(1) _{EBE [3:0]* pin numbers are 199-200, 203-204.}
(2) _{EAD [31:0] pin numbers are 144-146, 149-152, 145-155, 158-163, 166-170, 173-174, 176-180, 183-184, 187-189.}
(3) _{AD [31:0] pin numbers are 48-51, 54, 56-58, 61-62, 65-66, 69-72, 88, 90-94, 97, 99, 101-103, 105-109.}
(4) _{CBS [3.0]* pin numbers are 59, 74, 87,100.}
(5) _{An active low signal is denoted by a trailing asterisk (*).}
100660E
Conexant
1-17