CN8478 Datasheet, PDF (52/221 Pages) Conexant Systems, Inc – Multichannel Synchronous Communications Controller (MUSYCC)

2.0 Host Interface
2.2 PCI Configuration Registers
CN8478/CN8474A/CN8472A/CN8471A
Multichannel Synchronous Communications Controller (MUSYCC™)
Register 0, Address 00h
Table 2-10. Register 0, Address 00h
Bit
Field
Name
Reset
Value
31:16 _{Device ID}⁽¹⁾
847xh
15:0 _{Vendor ID}⁽¹⁾
14F1h
NOTE(S):
(1) _{Registers shared between Function 0 and 1.}
Type
RO
RO
Description
This unique device identification is assigned by the
manufacturer. This field always returns the value 847xh where x
can be 1, 2, 4, or 8 depending on the 32, 64, 128, or 256 channel
version of the device, respectively.
The unique vendor identification assigned to the manufacturer.
This field always returns the value 14F1h.
Register 1, Address 04h
The Status register records status information for PCI bus-related events. The
Command register provides coarse control to generate and respond to PCI
commands.
At reset, MUSYCC sets the bits in this register to 0. This means MUSYCC is
logically disconnected from the PCI bus for all cycle types except configuration
read and configuration write cycles.
Table 2-11. Register 1, Address 04h (1 of 2)
Bit
Field
Name
Reset
Value
31
Status
0
30
0
29
0
28
0
27
0
26:25
01b
24
0
23
01b
22
0
21
01b
20:16
0
Type
RR
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Description
Detected parity error. This bit is set by MUSYCC whenever it
detects a parity error on a data phase.
Unused.
Unused.
Unused.
Unused.
DEVSEL* timing. Indicates MUSYCC is a medium-speed device.
This means the longest time it will take MUSYCC to return
DEVSEL* when the EBUS is the target is 3 clock cycles.
Unused.
Fast back-to-back capable. Indicates that when the EBUS is a
target, it is capable of accepting fast back-to-back transactions
when the transactions are not to the same agent.
Unused.
Indicates the device is 66 MHz capable. This bit is set by
Revision C and later devices.
Unused.
2-14
Conexant
100660E