CN8478 Datasheet, PDF (159/221 Pages) Conexant Systems, Inc – Multichannel Synchronous Communications Controller (MUSYCC)

CN8478/CN8474A/CN8472A/CN8471A
Multichannel Synchronous Communications Controller (MUSYCC™)
6.0 Basic Operation
6.3 Channel Operation
For HDLC mode channels, data stream processing begins immediately upon
channel activation. Any type of alignment of a HDLC channel's data stream with
respect to its assigned serial port time slots is unnecessary, and MUSYCC
disables time slot synchronization for that channel. Therefore, no specific
alignment exists or needs to exist between the first bit of a HDLC message and
the first bit of the assigned channel time slot.
After activation of a Transparent mode channel, the SFALIGN setting selects
whether that channel's bit-level processor either waits for a frame synchronization
signal from the internal flywheel, or an external synchronization signal from the
serial port sync input pin before starting the data stream process. The selected
synchronization signal (internal or external) thus determines the alignment of that
channel's data stream with respect to its assigned serial port time slot. This time
slot alignment mechanism ensures Transparent mode channel's are able to
transfer sampled voice data streams to and from bytes stored in Shared Memory
while maintaining the alignment of those bytes with respect to the serial port time
slot. In Transparent mode MUSYCC is required to point to a MUSYCC-owned
buffer prior to a channel activation service request.
For Transparent mode hyperchannels, where multiple time slots are mapped to
a single channel, the first byte of data to and from the Shared Memory buffer is
aligned to the lowest numbered serial port time slot mapped to that hyperchannel.
If the lowest numbered time slot mapped to that hyperchannel equals time slot 12,
the bit-level processor aligns the first byte of Shared Memory buffer data to time
slot 12 and the next byte of data to the next higher numbered time slot that is also
mapped to that hyperchannel. This sequence of time slot mapped alignment is
true for all Transparent mode hyperchannel cases except when time slot 0 is the
lowest numbered time slot mapped. In which case, the first byte of Shared
Memory buffer data is transferred to the next higher numbered time slot. For
example, a Transparent mode hyperchannel mapped to time slot 0, and time slot 1
would output the first byte of Shared Memory data during time slot 1 and would
write receive data from time slot 1 into the first byte of the Shared Memory
buffer.
6.3.20 Descriptor Polling
Upon channel activation and any necessary frame alignment, MUSYCC must
fetch Message Descriptors from shared memory to start the flow of message bits
into and out of shared memory.
As a Buffer Descriptor is fetched, MUSYCC checks the owner-bit to verify if
the buffer is serviceable by MUSYCC. If the owner bit indicates that the host still
owns the buffer, the host has not yet prepared the data in the buffer for processing.
This may or may not be an error condition. In this case, MUSYCC also must
check the no-poll bit in the same descriptors to determine if polling for MUSYCC
ownership is enabled.
If the host owns the buffer and polling is disabled, the channel direction is
suspended from processing messages until the host intervenes with a subsequent
channel activation or channel jump request. The channel is not capable of leaving
this suspended state autonomously.
If the host owns the buffer and polling is enabled, the channel direction is
suspended from processing messages and MUSYCC periodically polls the owner
bit in the Buffer Descriptor to verify that the buffer is ready for MUSYCC. The
channel is capable of leaving this suspended state autonomously.
100660E
Conexant
6-25