CN8478 Datasheet, PDF (62/221 Pages) Conexant Systems, Inc – Multichannel Synchronous Communications Controller (MUSYCC)

3.0 Expansion Bus (EBUS)
3.1 Operation
CN8478/CN8474A/CN8472A/CN8471A
Multichannel Synchronous Communications Controller (MUSYCC™)
3.1 Operation
3.1.1 Initialization
At initialization, MUSYCC’s PCI Function 1 Configuration Space is initialized
with a value representing a 1 MB memory range assigned to MUSYCC’s EBUS.
This is detailed in Table 2-14, Register 4, Address 10h, and listed as
EBUS—Function 1 Base Address Register. An unmapped 1 MB system memory
range must be specified by assigning the upper 12 bits of the memory range to the
upper 12 bits of this register.
Command bit field memory space access control and optional parity error
response must be properly configured for MUSYCC to respond to EBUS
memory space accesses (see Table 2-4, Register 1, Address 04h).
On reset, MUSYCC disables EBUS memory space access. If the PCI attempts
to access EBUS memory space, there will be a PCI master-abort termination.
3.1.2 Address and Data
When MUSYCC’s host interface claims the cycle during a PCI access cycle, the
host interface compares the upper 12 bits of the PCI address lines to each of its
function’s base address registers. If signal lines AD[31:20] are identical to the
upper 12 bits of the Expansion Bus Base Address register, MUSYCC forwards
the access cycle to the EBUS interface within MUSYCC.
NOTE: Only single dword PCI operations can be performed when accessing the
EBUS.
MUYSCC accepts PCI slave burst write cycles to either function 0 or
function 1.
MUSYCC’s host interface has an internal 4-dword write FIFO buffer shared
by both functions; therefore a 1–4 dword burst write cycle can be performed to
either function. When the burst write data phase exceeds the length, MUSYCC
asserts a PCI target disconnect.
MUSYCC performs a PCI target disconnect after the first data phase of any
burst read cycle to either Function 0 or Function 1. Therefore, the PCI bridge
must be able to fragment a burst access into a single phase read or 1–4 phase burst
writes as controlled by the target disconnect.
Assuming the EBUS is connected to byte-wide peripheral devices, the EBUS
interface uses the lower 20 bits from PCI address lines AD[19:0] to construct a
byte address for the EBUS. Specifically, PCI address lines AD[19:2] are
converted to EBUS address lines EAD[17:0] by shifting out the two least
significant bits, AD[1:0]. This allows for byte-level addressing for up to 4
byte-wide devices on the EBUS. Given the above, the EBUS provides an 18-bit
addressing structure allowing byte addressing of up to four banks of 256 kB
address space each.
3-2
Conexant
100660E