CN8478 Datasheet, PDF (124/221 Pages) Conexant Systems, Inc – Multichannel Synchronous Communications Controller (MUSYCC)

5.0 Memory Organization
5.2 Descriptors
CN8478/CN8474A/CN8472A/CN8471A
Multichannel Synchronous Communications Controller (MUSYCC™)
5.2.5 Interrupt Level Descriptors
5.2.5.1 Interrupt Queue
Descriptor
MUSYCC generates interrupts for a variety of reasons. Interrupts are events or
errors detected by MUSYCC during bit-level processing of incoming serial data
streams. Interrupts are generated by MUSYCC and forwarded to the host for
servicing. Individual types of interrupts can be masked from being generated by
setting the appropriate interrupt mask or interrupt disable bit fields in various
descriptors. The interrupt mechanism, each individual interrupt, and interrupt
controlling mechanisms are discussed in this section.
MUSYCC employs a single Interrupt Queue Descriptor to communicate interrupt
information to the host. This descriptor is stored in MUSYCC in an internal
register. The descriptor in this register space stores the location and size of an
interrupt queue in shared memory. MUSYCC requires this information to transfer
interrupt descriptors it generates to shared memory for the host to use. MUSYCC
writes Interrupt Descriptors directly into the shared memory queue using PCI bus
master mode. MUSYCC’s PCI interface must be configured to allow bus
mastering.
The Interrupt Queue Descriptor is initialized by the host issuing a service
request to MUSYCC to read of a copy of the Interrupt Queue Descriptor from
shared memory. Another method of initialization is for the host to directly write
the information into the appropriate register space within MUSYCC.
Tables 5-28 through 5-30 list the details of the Interrupt Queue Descriptor.
Table 5-28. Interrupt Queue Descriptor
Byte Offset
Field Name
00h
Interrupt Queue Pointer
04h
Interrupt Queue Length
TOTAL
dwords
1
1
2
Octets
4
4
8
Table 5-29. Interrupt Queue Pointer
Bit
Field
Name
Value
Description
31:2 IQPTR[30:0]
1:0
IQPTR[1:0]
These 30 bits are appended with 00b to form a dword-aligned 32-bit address. This
address points to the first word of the Interrupt Queue buffer.
0
Ensures dword alignment.
Table 5-30. Interrupt Queue Length
Bit
Field
Name
Value
31:15
RSVD
0
14:0 IQLEN[14:0]
Description
Reserved.
This 15-bit number specifies the length of the Interrupt Queue buffer in dwords. The
maximum size for an interrupt queue is 32,768 dwords. This is a 0-based number. A
value of 1 indicates the queue length is 2 descriptors long, the required minimum.
5-38
Conexant
100660E