CN8478 Datasheet, PDF (111/221 Pages) Conexant Systems, Inc – Multichannel Synchronous Communications Controller (MUSYCC)

CN8478/CN8474A/CN8472A/CN8471A
Multichannel Synchronous Communications Controller (MUSYCC™)
Table 5-16. Transmit or Receive Subchannel Map
Byte Offset
MSB
00h
Ch0, Bit 3
04h
Ch0, Bit 7
08h
Ch1, Bit 3
0Ch
Ch1, Bit 7
...
....
...
....
F8h
Ch31, Bit 3
FCh
Ch31, Bit 7
Ch0, Bit 2
Ch0, Bit 6
Ch1, Bit 2
Ch1, Bit 6
....
....
Ch31, Bit 2
Ch31, Bit 6
5.0 Memory Organization
5.2 Descriptors
Ch0, Bit 1
Ch0, Bit 5
Ch1, Bit 1
Ch1, Bit 5
....
....
Ch31, Bit 1
Ch31, Bit 5
LSB
Unused
Ch0, Bit 4
Unused
Ch1, Bit 4
...
...
Unused
Ch31, Bit 4
Table 5-17. Subchannel Descriptor
Bit Field
Name
31
BITEN3/7
30:29
28:24
23
RSVD
CH3[4:0]
BITEN2/6
22:21
20:16
15
RSVD
CH2[4:0]
BITEN1/5
14:13
12:8
7
RSVD
CH1[4:0]
BITEN0/3
6:5
RSVD
4:0
CH0[4:0]
Value
0
1
0
0–31
0
1
0
0–31
0
1
0
0–31
0
1
0
0–31
Description
Bit disabled.
Bit enabled.
Reserved.
Channel number assigned to this bit.
Bit disabled.
Bit enabled.
Reserved.
Channel number assigned to this bit.
Bit disabled.
Bit enabled.
Reserved.
Channel number assigned to this bit.
Bit disabled.
Bit enabled.
Reserved.
Channel number assigned to this bit.
To enable the subchanneling feature, both the Time Slot Map and the
Subchannel Map must be copied into MUSYCC’s internal registers because it is
from here time slot-to-channel mapping and channel-to-subchannel mapping is
decoded. The host can instruct MUSYCC to read in the maps from shared
memory by issuing the appropriate service request; otherwise, the host must
perform multiple direct writes into MUSYCC’s internal registers by appropriately
addressing PCI access cycles for MUSYCC.
100660E
Conexant
5-25