CN8478 Datasheet, PDF (125/221 Pages) Conexant Systems, Inc – Multichannel Synchronous Communications Controller (MUSYCC)

CN8478/CN8474A/CN8472A/CN8471A
Multichannel Synchronous Communications Controller (MUSYCC™)
5.0 Memory Organization
5.2 Descriptors
5.2.5.2 Interrupt
Descriptor
The Interrupt Descriptor describes the format of data transferred into the queue.
This 32-bit word includes bit fields for the following:
• Identifying the interrupt source from within MUSYCC. Channel group
number (0–8), channel number (0–31), and direction (receive or transmit)
are provided. There are 256 possible channel sources.
• Events assisting the host in synchronizing channel activities.
• Errors and unexpected conditions resulting in lost data, discontinued
message processing, or prevented successful completion of a service
request.
• Number of bytes transferred to or from shared memory when a memory
buffer has been completely processed.
All interrupts are associated with a channel group, channel number, and
direction of the channel with the following exceptions:
1. When an OOF or COFA condition is detected on a serial port, only one
interrupt is generated for the entire group until the condition is cleared and
the condition reoccurs. The group is identified by the GRP field, and the
direction is identified by the DIR field. The CH field is the channel
number currently being serviced when this condition is detected.
2. The ILOST interrupt bit indicates that one or more interrupt was lost
internally due to a lack of internal queuing space. This occurs when
MUSYCC generates more interrupt descriptors than can be stored in the
Interrupt Queue in shared memory. The latency of host processing of the
Interrupt Queue can also be a factor. This condition is conveyed by
MUSYCC overwriting the ILOST bit field in the last interrupt descriptor
in an internal queue prior to being transferred to shared memory. The bit
field is not specific to or associated with the interrupt descriptor being
overwritten. Only one bit is overwritten, and the integrity of the original
descriptor is maintained.
3. The PERR interrupt bit indicates that MUSYCC detected a parity error
during a PCI access cycle. This condition is conveyed by MUSYCC
overwriting the PERR bit field in the last interrupt descriptor in an internal
queue prior to being transferred to shared memory. The bit field is not
specific to or associated with the interrupt descriptor being overwritten.
Only one bit is overwritten and the integrity of the original descriptor is
maintained.
Interrupt descriptors can convey certain combinations of events and errors,
but no more than one event and one error. Because multiple information can be
conveyed via a single interrupt descriptor, always look at both the event and error
fields when servicing interrupt descriptors. Following is a list of possible
combinations of events and errors.
100660E
Conexant
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