EP2C8T144C8N Datasheet, PDF (64/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

I/O Structure & Features
Figure 2–20. Cyclone II IOE Structure
Logic Array
OE Register
OE
Output
Output Register
Input (1)
Input Register
Note to Figure 2–20:
(1) There are two paths available for combinational or registered inputs to the logic
array. Each path contains a unique programmable delay chain.
The IOEs are located in I/O blocks around the periphery of the Cyclone II
device. There are up to five IOEs per row I/O block and up to four IOEs
per column I/O block (column I/O blocks span two columns). The row
I/O blocks drive row, column (only C4 interconnects), or direct link
interconnects. The column I/O blocks drive column interconnects.
Figure 2–21 shows how a row I/O block connects to the logic array.
Figure 2–22 shows how a column I/O block connects to the logic array.
2–38
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007