EP2C8T144C8N Datasheet, PDF (190/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Cyclone II PLL Hardware Overview
The VCO frequency is a critical parameter that must be between 300 and
1,000 MHz to ensure proper operation of the PLL. The Quartus II
software automatically sets the VCO frequency within the recommended
range based on the clock output and phase-shift requirements in your
design.
PLL Reference Clock Generation
In Cyclone II devices, up to four clock pins can drive the PLL, as shown
in Figure 7–11 on page 7–26. The multiplexer output feeds the PLL
reference clock input. The PLL has internal delay elements that
compensate for the clock delay from the input pin to the clock input port
of the PLL.
Table 7–3 shows the clock input pin connections to the PLLs in the
Cyclone II device.
Table 7–3. PLL Clock Input Pin Connections
Device
EP2C5
EP2C8
EP2C15
EP2C20
EP2C35
EP2C50
EP2C70
PLL 1
PLL 2
PLL 3
PLL 4
CLK0 CLK2 CLK4 CLK6 CLK8 CLK10 CLK12 CLK14
CLK1 CLK3 CLK5 CLK7 CLK9 CLK11 CLK13 CLK15
vvvv
vvvv
vvvvvvvv
vvvvvvvv
vvvvvvvv
vvvvvvvv
vvvvvvvv
Each PLL can be fed by one of four single-ended or two differential clock
input pins. For example, PLL 1 can be fed by CLK[3..0] when using a
single-ended I/O standard. When your design uses a differential I/O
standard, these same clock pins have a secondary function as
LVDSCLK[2..1]p and LVDSCLK[2..1]n pins. When using differential
clocks, the CLK0 pin’s secondary function is LVDSCLK1p, the CLK1 pin’s
secondary function is LVDSCLK1n, etc.
7–6
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007