EP2C8T144C8N Datasheet, PDF (386/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

PS Configuration
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All information in the “Single Device PS Configuration Using a MAX II
Device as an External Host” on page 13–22 section is also applicable
when using a microprocessor as an external host. Refer to that section for
all configuration information.
The MicroBlaster™ software driver allows you to configure Altera
FPGAs, including Cyclone II devices, through the ByteBlaster II or
ByteBlasterMV cable in PS mode. The MicroBlaster software driver
supports a RBF programming input file and is targeted for embedded PS
configuration. The source code is developed for the Windows NT
operating system, although you can customize it to run on other
operating systems.
1 Since the Cyclone II device can decompress the compressed
configuration data on-the-fly during PS configuration, the
MicroBlaster software can accept a compressed RBF file as its
input file.
For more information on the MicroBlaster software driver, see the
Configuring the MicroBlaster Passive Serial Software Driver White Paper and
source files on the Altera web site at www.altera.com.
If you turn on the Enable user-supplied start-up clock (CLKUSR) option
in the Quartus II software, the Cyclone II devices does not enter user
mode after the MicroBlaster has transmitted all the configuration data in
the RBF file. You need to supply enough initialization clock cycles to
CLKUSR pin to enter user mode.
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Single Device PS Configuration Using a Configuration Device
You can use an Altera configuration device (for example, an EPC2, EPC1,
or enhanced configuration device) to configure Cyclone II devices using
a serial configuration bitstream. Configuration data is stored in the
configuration device. Figure 13–13 shows the configuration interface
connections between the Cyclone II device and a configuration device.
1 The figures in this chapter only show the configuration-related
pins and the configuration pin connections between the
configuration device and the FPGA.
For more information on enhanced configuration devices and flash
interface pins (e.g., PGM[2..0], EXCLK, PORSEL, A[20..0], and
DQ[15..0]), see the Enhanced Configuration Devices (EPC4, EPC8 &
EPC16) Data Sheet.
13–32
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007