EP2C8T144C8N Datasheet, PDF (53/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Cyclone II Architecture
Figure 2–16 shows a block diagram of the Cyclone II PLL.
Figure 2–16. Cyclone II PLL Note (1)
CLK0 (1)
CLK1
CLK2 (1)
CLK3
Manual Clock
Switchover
Select Signal
inclk0
f_IN
inclk1
Reference
Input Clock
f_REF = f_IN /n
÷n
PFD
up
down
Charge
Pump
f_FB
Loop
Filter
÷m
VCO Phase Selection
Selectable at Each
PLL Output Port
Post-Scale
Counters
8
f_VCO
8
VCO ÷k
(3)
8
÷c0
Global
Clock
Global
÷c1
Clock
÷c2
Global
(2)
Clock
PLL<#>_OUT
Lock Detect
& Filter
To I/O or
general routing
Notes to Figure 2–16:
(1) This input can be single-ended or differential. If you are using a differential I/O standard, then two CLK pins are
used. LVDS input is supported via the secondary function of the dedicated CLK pins. For example, the CLK0 pin’s
secondary function is LVDSCLK1p and the CLK1 pin’s secondary function is LVDSCLK1n. If a differential I/O
standard is assigned to the PLL clock input pin, the corresponding CLK(n) pin is also completely used. The
Figure 2–16 shows the possible clock input connections (CLK0/CLK1) to PLL1.
(2) This counter output is shared between a dedicated external clock output I/O and the global clock network.
f
For more information on Cyclone II PLLs, see the PLLs in the Cyclone II
Devices chapter in Volume 1 of the Cyclone II Device Handbook.
Embedded
Memory
The Cyclone II embedded memory consists of columns of M4K memory
blocks. The M4K memory blocks include input registers that synchronize
writes and output registers to pipeline designs and improve system
performance. The output registers can be bypassed, but input registers
cannot.
Altera Corporation
February 2007
2–27
Cyclone II Device Handbook, Volume 1