EP2C8T144C8N Datasheet, PDF (337/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

High-Speed Differential Interfaces in Cyclone II Devices
Table 11–5 defines the parameters of the timing diagram shown in
Figure 11–16. Figure 11–17 shows the Cyclone II high-speed I/O timing
budget.
Table 11–5. High-Speed I/O Timing Definitions
Parameter
Symbol
Description
Transmitter channel-to-
channel skew (1)
Sampling window
TCCS
SW
Receiver input skew margin RSKM
Input jitter tolerance (peak-
to-peak)
Output jitter (peak-to-peak)
The timing difference between the fastest and slowest output edges,
including t_CO variation and clock skew. The clock is included in the
TCCS measurement.
The period of time during which the data must be valid in order for you
to capture it correctly. The setup and hold times determine the ideal
strobe position within the sampling window.
T_SW = T_SU + T_hd + PLL jitter.
RSKM is defined by the total margin left after accounting for the
sampling window and TCCS. The RSKM equation is: RSKM = (TUI
– SW – TCCS) / 2.
Allowed input jitter on the input clock to the PLL that is tolerable while
maintaining PLL lock.
Peak-to-peak output jitter from the PLL.
Note to Table 11–5:
(1) The TCCS specification applies to the entire bank of LVDS as long as the SERDES logic are placed within the LAB
adjacent to the output pins.
Figure 11–16. High-Speed I/O Timing Diagram
External
Input Clock
Time Unit Interval (TUI)
Internal Clock
Receiver
Input Data
TCCS RSKM
Sampling Window (SW)
RSKM TCCS
Altera Corporation
February 2007
11–15
Cyclone II Device Handbook, Volume 1