EP2C8T144C8N Datasheet, PDF (188/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Cyclone II PLL Hardware Overview
The loop filter converts these up and down signals to a voltage that is
used to bias the VCO. If the charge pump receives a logic high on the up
signal, current is driven into the loop filter. If the charge pump receives a
logic high on the down signal, current is drawn from the loop filter. The
loop filter filters out glitches from the charge pump and prevents voltage
over-shoot, which minimizes the jitter on the VCO.
The voltage from the charge pump determines how fast the VCO
operates. The VCO is implemented as an four-stage differential ring
oscillator. A divide counter, m, is inserted in the feedback loop to increase
the VCO frequency above the input reference frequency, making the VCO
frequency f_VCO = m × f_REF. Therefore, the feedback clock, f_FB, applied to
one input of the PFD, is locked to the input reference clock, f_REF (f_IN/n),
applied to the other input of the PFD.
The VCO output can feed up to three post-scale counters (c0, c1, and c2).
These post-scale counters allow a number of harmonically related
frequencies to be produced by the PLL.
Additionally, Cyclone II PLLs have internal delay elements to
compensate for routing on the global clock networks and I/O buffers.
These internal delays are fixed and not accessible to the user.
Figure 7–2 shows a simplified block diagram of the major components of
a Cyclone II device PLL.
7–4
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007