EP2C8T144C8N Datasheet, PDF (115/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

DC Characteristics and Timing Specifications
Table 5–9. DC Characteristics for User I/O Pins Using Differential I/O Standards Note (1) (Part 2 of 2)
I/O Standard
Differential 1.8-V
HSTL class I
and II (3)
Differential
SSTL-2 class I
(4)
Differential
SSTL-2 class II
(4)
Differential
SSTL-18 class I
(4)
Differential
SSTL-18 class II
(4)
V_OD (mV)
ΔV_OD (mV)
Min Typ Max Min Max
— — — ——
V_OCM (V)
Min Typ Max
—
—
—
V_OH (V)
Min Max
V_{C C I O} —
– 0.4
— — — —— —
—
— V_{T T} + —
0.57
— — — —— —
—
— V_{T T} + —
0.76
— — — — — 0.5 × 0.5 × 0.5 × V_{T T} + —
V_{C C I O} V_{C C I O} V_{C C I O} 0.475
–
+
0.125
0.125
—
—
— — — 0.5 × 0.5 × 0.5 × V_{C C I O} —
V_{C C I O} V_{C C I O} V_{C C I O} – 0.28
–
+
0.125
0.125
V_OL (V)
Min Max
— 0.4
— V_{T T} –
0.57
— V_{T T} –
0.76
— V_{T T} –
0.475
— 0.28
Notes to Table 5–9:
(1) The LVPECL I/O standard is only supported on clock input pins. This I/O standard is not supported on output
pins.
(2) The RSDS and mini-LVDS I/O standards are only supported on output pins.
(3) The differential 1.8-V HSTL and differential 1.5-V HSTL I/O standards are only supported on clock input pins and
PLL output clock pins.
(4) The differential SSTL-18 and SSTL-2 I/O standards are only supported on clock input pins and PLL output clock
pins.
DC
Characteristics
for Different Pin
Types
Table 5–10 shows the types of pins that support bus hold circuitry.
Table 5–10. Bus Hold Support
Pin Type
I/O pins using single-ended I/O standards
I/O pins using differential I/O standards
Dedicated clock pins
JTAG
Configuration pins
Bus Hold
Yes
No
No
No
No
Altera Corporation
February 2008
5–11
Cyclone II Device Handbook, Volume 1