EP2C8T144C8N Datasheet, PDF (237/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Cyclone II Memory Blocks
applications require local data storage, traditionally implemented with
standard flip-flops that quickly exhaust many logic cells for large shift
registers. A more efficient alternative is to use embedded memory as a
shift register block, which saves logic cell and routing resources.
The size of a (w × m × n) shift register is determined by the input data
width (w), the length of the taps (m), and the number of taps (n), and must
be less than or equal to the maximum number of memory bits, which is
4,608 bits. In addition, the size of (w × n) must be less than or equal to the
maximum width of the block, which is 36 bits. If a larger shift register is
required, the memory blocks can be cascaded.
Data is written into each address location at the falling edge of the clock
and read from the address at the rising edge of the clock. The shift register
mode logic automatically controls the positive and negative edge
clocking to shift the data in one clock cycle. Figure 8–12 shows the
Cyclone II memory block in the shift register mode.
Figure 8–12. Cyclone II Shift Register Mode Configuration
w × m × n Shift Register
m-Bit Shift Register
W
W
m-Bit Shift Register
W
W
m-Bit Shift Register
W
m-Bit Shift Register
W
n Number of Taps
W
W
Altera Corporation
February 2008
8–15
Cyclone II Device Handbook, Volume 1