EP2C8T144C8N Datasheet, PDF (268/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

DDR Memory Interface Pins
For example, to implement a 72-bit wide SDRAM memory interface in
Cyclone II devices, use 5 DQS/DQ groups in the top I/O bank and 4
DQS/DQ groups in the bottom I/O bank, or vice-versa. In this case, if
DQS0T or DQS1T is used for the fifth DQS signal, the DQS2R or DQS2L
pins become regular I/O pins and are unavailable for DQS signals in
memory interface. For detailed information about the global clock
network, refer to the Global Clock Network & Phase Locked Loops section in
the Cyclone II Architecture chapter of the Cyclone II Device Handbook.
You must configure the DQ and DQS pins as bidirectional DDR pins on
all the I/O banks of the device. Use the altdq and altdqs
megafunctions to configure the DQ and DQS paths, respectively. If you
only want to use the DQ or DQS pins as inputs, for instance in the QDRII
memory interface where DQ and DQS are unidirectional read data and
read clock, set the output enable of the DQ or DQS pins to ground. For
further information, please refer to the section “QDRII SRAM” on
page 9–5 of this handbook.
Clock, Command & Address Pins
You can use any of the user I/O pins on all the I/O banks (that support
the external memory’s I/O standard) of the device to generate clocks and
command and address signals to the memory device.
Parity, DM & ECC Pins
You can use any of the DQ pins for the parity pins in Cyclone II devices.
Cyclone II devices support parity in the ×8/×9 and ×16/×18 modes.
There is one parity bit available per 8 bits of data pins.
The data mask (DM) pins are required when writing to DDR SDRAM and
DDR2 SDRAM devices. A low signal on the DM pin indicates that the
write is valid. If the DM signal is high, the memory masks the DQ signals.
In Cyclone II devices, the DM pins are pre-assigned in the device pin outs,
and these are the preferred pins. Each group of DQS and DQ signals
requires a DM pin. Similar to the DQ output signals, the DM signals are
clocked by the –90° shifted clock.
Some DDR SDRAM and DDR2 SDRAM devices support error correction
coding (ECC) or parity. Parity bit checking is a way to detect errors, but it
has no correction capabilities. ECC can detect and automatically correct
errors in data transmission. In 72-bit DDR SDRAM, there are 8 ECC pins
on top of the 64 data pins. Connect the DDR and DDR2 SDRAM ECC pins
to a Cyclone II device’s DQS/DQ group. The memory controller needs
extra logic to encode and decode the ECC data.
9–14
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007