EP2C8T144C8N Datasheet, PDF (252/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Conclusion
Figure 8–24. Cyclone II Mixed-Port Read-During-Write: Don’t Care Mode Note (1)
inclock
address_a and
address_b
data_a A
wren_a
wren_b
q_b
Note to Figure 8–24:
(1) Outputs are not registered.
Address Q
B
Unknown
B
Mixed-port read-during-write is not supported when two different clocks
are used in a dual-port RAM. The output value is unknown during a
mixed-port read-during-write operation.
Conclusion
The M4K memory structure of Cyclone II devices provides a flexible
memory architecture with high memory bandwidth. It addresses the
needs of different memory applications in FPGA designs with features
such as different memory modes, byte enables, parity bit storage, address
clock enables, mixed clock mode, shift register mode, mixed-port width
support, and true dual-port mode.
Referenced
Documents
This chapter references the following documents:
■ Cyclone II Device Family Data Sheet in volume 1 of the Cyclone II Device
Handbook
■ Single- and Dual-Clock FIFO Megafunction User Guide
■ Using Parity to Detect Errors White Paper
8–30
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2008