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EP2C8T144C8N Datasheet, PDF (227/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1 | |||
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Cyclone II Memory Blocks
case writing is controlled only by the write enable signals. There is no
clear port to the byte enable registers. M4K blocks support byte enables
when the write port has a data width of 1, 2, 4, 8, 9, 16, 18, 32, or 36 bits.
When using data widths of 1, 2, 4, 8, and 9 bits, the byte enable behaves
as a redundant write enable because the data width is less than or equal
to a single byte. Table 8â3 summarizes the byte selection.
Table 8â3. Byte Enable for Cyclone II M4K Blocks Note (1)
byteena[3..0]
[0] = 1
[1] = 1
[2] = 1
[3] = 1
datain
Ã1
[0]
-
-
-
datain
Ã2
[1..0]
-
-
-
datain
Ã4
[3..0]
-
-
-
Affected Bytes
datain
Ã8
[7..0]
-
-
-
datain
Ã9
[8..0]
-
-
-
datain
à 16
[7..0]
[15..8]
-
-
Note to Table 8â3:
(1) Any combination of byte enables is possible.
datain
à 18
[8..0]
[17..9]
-
-
datain
à 32
[7..0]
[15..8]
[23..16]
[31..24]
datain
à 36
[8..0]
[17..9]
[26..18]
[35..27]
Table 8â4 shows the byte enable port control for true dual-port mode.
Table 8â4. Byte Enable Port Control for True Dual-Port Mode
byteena [3:0]
[1:0]
[3:2]
Affected Port
Port A (1)
Port B (1)
Note to Table 8â4:
(1) For any data width up to Ã18 for each port.
Figure 8â2 shows how the wren and byteena signals control the
operations of the RAM.
When a byte enable bit is de-asserted during a write cycle, the
corresponding data byte output appears as a âdonât careâ or unknown
value. When a byte enable bit is asserted during a write cycle, the
corresponding data byte output is the newly written data.
Altera Corporation
February 2008
8â5
Cyclone II Device Handbook, Volume 1
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