EP2C8T144C8N Datasheet, PDF (161/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

DC Characteristics and Timing Specifications
Figure 5–4. High-Speed I/O Timing Budget Note (1)
Internal Clock Period
0.5 × TCCS RSKM
SW
Note to Figure 5–4:
(1) The equation for the high-speed I/O timing budget is:
period = TCCS + RSKM + SW + RSKM.
RSKM 0.5 × TCCS
Table 5–48 shows the RSDS timing budget for Cyclone II devices at
311 Mbps. RSDS is supported for transmitting from Cyclone II devices.
Cyclone II devices cannot receive RSDS data because the devices are
intended for applications where they will be driving display drivers.
Cyclone II devices support a maximum RSDS data rate of 311 Mbps using
DDIO registers. Cyclone II devices support RSDS only in the commercial
temperature range.
Table 5–48. RSDS Transmitter Timing Specification (Part 1 of 2)
Symbol Conditions
f_{H S C L K}
×10
(input
×8
clock
frequency)
×7
×4
×2
×1
Device
×10
operation
×8
in Mbps
×7
×4
×2
×1
t_{D U T Y}
—
–6 Speed Grade
Min Typ Max(1)
10 — 155.5
10 — 155.5
10 — 155.5
10 — 155.5
10 — 155.5
10 — 311
100 — 311
80 — 311
70 — 311
40 — 311
20 — 311
10 — 311
45 — 55
–7 Speed Grade
Min Typ Max(1)
10 — 155.5
10 — 155.5
10 — 155.5
10 — 155.5
10 — 155.5
10 — 311
100 — 311
80 — 311
70 — 311
40 — 311
20 — 311
10 — 311
45 — 55
–8 Speed Grade
Unit
Min Typ Max(1)
10 — 155.5 MHz
10 — 155.5 MHz
10 — 155.5 MHz
10 — 155.5 MHz
10 — 155.5 MHz
10 — 311 MHz
100 — 311 Mbps
80 — 311 Mbps
70 — 311 Mbps
40 — 311 Mbps
20 — 311 Mbps
10 — 311 Mbps
45 — 55
%
Altera Corporation
February 2008
5–57
Cyclone II Device Handbook, Volume 1