EP2C8T144C8N Datasheet, PDF (269/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

External Memory Interfaces
Phase Lock Loop (PLL)
When using the Cyclone II I/O banks to interface with the DDR memory,
at least one PLL with two outputs is needed to generate the system clock
and the write clock. The system clock generates the DQS write signals,
commands, and addresses. The write clock shifts by –90° from the system
clock and generates the DQ signals during writes.
Clock Delay Control
Clock delay control circuit on each DQS pin allows a phase shift that
center-aligns the incoming DQS signals within the data window of their
corresponding DQ data signals. The phase-shifted DQS signals drive the
global clock network. This global DQS signal then clocks the DQ signals
on internal LE registers. The clock delay control circuitry is used during
the read operations where the DQS signals are acting as input clocks or
strobes.
Figure 9–8 illustrates DDR SDRAM interfacing from the I/O pins
through the dedicated circuitry to the logic array.
Figure 9–8. DDR SDRAM Interfacing
DQS
DQ
OE
LE
Register
LE
Register
VCC
LE
Register
OE
LE
Register
t
LE
Register
DataA
LE
Register
LE
Register
Adjacent LAB LEs
LE
Register
GND
LE
Register
clk
PLL
-90˚ Shifted clk
Clock Delay
Control Circuitry
DataB
LE
Register
en/dis
Global Clock
Clock Control
Block
ENOUT
Dynamic Enable/Disable
Circuitry
ena_register_mode
LE
Register
LE
Register
LE
Register
Resynchronizing
to System Clock
Figure 9–1 on page 9–4 shows an example where the DQS signal is shifted
by 90°. The DQS signal goes through the 90° shift delay set by the clock
delay control circuitry and global clock routing delay from the clock delay
control circuitry to the DQ LE registers. The DQ signals only goes through
routing delays from the DQ pin to the DQ LE registers. The delay from
Altera Corporation
February 2007
9–15
Cyclone II Device Handbook, Volume 1